Follow @IARPAnewsCryogenic Computing Complexity (C3) Program
Power and cooling for large-scale computing systems are rapidly becoming unmanageable problems for the enterprises which depend on them. The trend towards large, centralized computing facilities to house supercomputers, data centers, and special purpose computers continues to grow, driven by cloud computing, support of mobile devices, Internet traffic volume, and computation-intensive applications. In 2012, the total power demand of the TOP500 supercomputers measured around 0.25 GW; the total power usage of the, roughly, 500,000 data centers worldwide was estimated to be 31 GW in 2011. Conventional computing systems, which are based on complementary metal-oxide-semiconductor (CMOS) switching devices and normal metal interconnects, appear to have no path to be able to increase energy efficiency fast enough to keep up with increasing demands for computation.
Superconducting computing could offer an attractive low-power alternative to CMOS with many potential advantages. Josephson junctions, the superconducting switching devices, switch quickly (~1 ps), dissipate little energy per switch (< 10^-19 J), and communicate information via small current pulses that propagate over superconducting transmission lines nearly without loss. While, in the past, significant technical obstacles prevented serious exploration of superconducting computing, recent innovations have created foundations for a major breakthrough. For example, the new single flux quantum (SFQ) logic circuits have no static power dissipation, and new energy efficient cryogenic memory ideas allow operation of memory and logic within the cold environment. Studies indicate that superconducting supercomputers may be capable of 1 PFLOP/s for about 25 kW and 100 PFLOP/s for about 200 kW, including the cryogenic cooler. Proof at smaller scales is an essential first step before any attempt to build a supercomputer.
Superconducting computing research currently consists of a few, scattered efforts with no initiative focused on advancing the field overall. Major research challenges include insufficient memory, insufficient integration density, and no realization of complete computing systems. The C3 Program will address these challenges with the goal of establishing superconducting computing as a long-term solution to the power- cooling problem and a successor to end-of-roadmap CMOS for high performance computing. Success of C3 will pave the way to a new generation of superconducting computers that are far more energy efficient than end-of-roadmap CMOS and scalable to practical application.
IARPA expects that the C3 program will be a five-year, two-phase program. Phase one, which encompasses the first three years, serves primarily to develop the technologies that are required to demonstrate a small superconducting processor. Phase two, for the final two years, will integrate those new technologies into a small-scale working model of a superconducting computer.
C3 Program thrusts will include:
1. Cryogenic memory: New approaches to enable high performance computing systems with greatly improved memory capacity and energy efficiency.
2. Logic, communications and systems: Development of advanced superconducting circuits and integration with memory and other components for demonstration of a limited superconducting computer system on which to measure performance metrics.
IARPA expects that each proposal will address fully a single thrust. If a proposer wishes to propose against more than one thrust, then separate proposals should be submitted. Proposals are not desired that address only a small portion of a thrust’s goals. Collaborative efforts and teaming among potential performers will be strongly encouraged. Participation is open to individuals and organizations from around the world so long as the prime contractor is a US organization.
