Information Microsystems

Precise timing is essential across DoD systems, including communications, navigation, electronic warfare, intelligence systems reconnaissance, and system-of-systems platform coordination, as well as in national infrastructure applications in commerce and banking, telecommunications, and power distribution. Improved clock performance throughout the timing network, particularly at point-of-use, would enable advanced collaborative capabilities and provide greater resilience to disruptions of timing synchronization networks, notably by reducing reliance on satellite-based global navigation satellite system (GNSS) timing signals.

The explosive growth in mobile and telecommunication markets has pushed the semiconductor industry toward integration of digital, analog, and mixed-signal blocks into system-on-chip (SoC) solutions. Advanced silicon (Si) complementary metal oxide semiconductor (CMOS) technology has enabled this integration, but has also led to a rise in costs associated with design and processing. Driven by aggressive digital CMOS scaling for high-volume products, Intellectual Property (IP) reuse has emerged as a tool to help lower design costs associated with advanced SoCs.

Radio Frequency and mixed signal electronics face performance limitations due to the limited circuit complexity possible in typical high-speed/high-dynamic-range compound semiconductor integrated circuit technologies.

Radio Frequency and mixed signal electronics face performance limitations due to the limited circuit complexity possible in typical high-speed/high-dynamic-range compound semiconductor integrated circuit technologies. By integrating these high-performance electronics with deep submicron silicon complementary metal-oxide semiconductor (Si CMOS) technology, designers can exploit the ultra large scale integration density of Si CMOS to combine complex signal processing and self-correction architectures with the highest performance compound semiconductor electronics, thus achieving unprecedented levels of performance (e.g. bandwidth, dynamic range, power consumption).

High performance optoelectronic systems, e.g. ultra low-noise lasers and optoelectronic signal sources, are employed in numerous applications such as fiber optic communications, high-precision timing references, LADAR, imaging arrays, etc. Current state-of-the-art ultra-low noise lasers and optoelectronic signal sources use macro-scale photonics for mechanical and thermal noise suppression, and off-chip electronics for feedback control. The benchtop or rack mount component-level assembly of these sources limits photonic coupling efficiency as well as the speed of electronic feedback, and also adds size and weight to the system. Integration of these components in a chip-scale form factor could greatly mitigate these limitations.