Presentations from the 2005 International Conference on Characterization and Metrology for ULSI Technology
Because of the large interest in the talks given at this Conference and as a service to the semiconductor community, the organizers have made the slides from many of the talks presented available here. These slides should be considered the sole property of the speaker. Please do not alter or reproduce any of the slides presented.
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The Conference organizers would like to thank each of the speakers who have made their slides available!
- Design for Manufacture in Overlay Metrology
Mike Adel, KLA Tencor
- Recent Advances in Semiconductor X-ray Metrology
Dileep Agnihotri, Jordan Valley Semiconductors, Inc.
- Profiling High-k Dielectrics with Sub-nanometric Depth Resolution
Israel Baumvol, Universidade Federal do Rio Grande do Sul, Porto Allegre, Brazil
- Applying Semiconductor Technologies and Metrology Tools to Biomedical Research: Manipulation and Detection of Single Molecules
Andrew Berlin, Intel
- Recent Developments in Electrical Metrology for MOS Fabrication
George Brown (ISMT) and Bob Hillard (SSM)
- Metrology (Including Materials Characterization) for Nanoelectronics
Alain Diebold, ISMT
- Growth and Characterization of Ultrathin Metal Films for ULSI Interconnects
John Ekerdt, UT-Austin
- Low-k Materials for ULSI Applications
Don Frye, Dow
- Interfaces Issues in Alternative Gate Stack Structures
Eric Garfunkel, Rutgers
- Ultra-precision CD Metrology for Sub-100 nm Pattern by AFM
Satoshi Gonda, National Institute of Advanced Industrial Science and Technology, Ibaraki, Japan
- Challenges of Smaller Particle Detection on Both Bulk-Silicon and SOI Wafers
Takeshi Hattori, Sony Semiconductor, Atsugi, Japan
- Recent Advances in Lithography and High Level Metrology Needs for Lithography
Scott Hector, Freescale Assignee to ISMT
- Welcome
Bob Helms, Dean, Erik Jonsson School of Engineering & Comp. Sci., UTD
- The R&D Crisis: It's Growing Too Fast and We Need to Act on It
Dan Hutcheson, VLSI Research, Inc.
- The Aberration Corrected SEM
David Joy, ORNL/UT
- High Resolution (Analytical) TEM for Nano-electronic Materials Research
Moon Kim, UT Dallas
- The Role of a Physical Analysis Laboratory in a 300 mm IC Development & Manufacturing Center
Laurens Kwakman, Philips Crolles II
- Inelastic Electron Tunneling Spectroscopy (IETS) of High-k Dielectrics
T.P. Ma, Yale
- Aggressive Scaling of Cu-low-k Interconnects
Karen Maex, IMEC
- The Interconnect Era of Gigascale Integration
James Meindl, Georgia Tech.
- X-ray Photoelectron Spectroscopy of High-k Dielectrics
Bob Opila, University of DE
- Source/Drain Junctions and Contacts for 45 nm CMOS and Beyond
Mehmet Öztürk, NCSU
- The Opportunities and Challenges of Bringing New Metrology Equipment to Market
Dave Perloff, ReVera, Incorporated
- Collaboration: The Semiconductor Industry's Path to Survival and Growth
Mike Polcari, ISMT
- Overview of Scatterometry Applications in High Volume Silicon Manufacturing
Chris Raymond, Accent
- Optical Technologies Limits of CD Metrology
Bryan Rice, Intel
- The Relation Between Crystalline Phase, Electronic Structure and Dielectric Properties in High-k Gate Stacks
Safak Sayan, Rutgers University
- Atomic Layer Deposition of High k Dielectric and Metal Gate Stacks for MOS Devices
Yoshi Senzaki, ISMT
- Advanced EELS Applications in Process Development
Heiko Stegmann, AMD Saxony, Dresden, Germany
- Economies of CMOS Scaling
Hans Stork, Texas Instruments
- Mask Inspection Technology for 65 nm Technology Node and Beyond
Toru Tojo, Topcon Corporation, Tokyo, Japan
- Three Dimensional Characterization of Semiconductor Interfaces Using Aberration-corrected Scanning Transmission Electron Microscopy
Klaus van Benthem, ORNL
- Metrology Challenges for 45 nm Strained-Si Devices
Victor Vartanian, Freescale
- Issues in Line Edge and Line Width Roughness Metrology
John Villarrubia and Andras Vladar, NIST
- Metrology for Emerging Research Devices and Materials
Eric Vogel, NIST
- Starting Materials and Functional Layers for The 2005 International Technology Roadmap for Semiconductors: Challenges and Opportunities
Mike Walden, SUMCO USA, and Howard Huff, ISMT
- On-line Detection and Measurement of Molecular Contamination in Semiconductor Processing Solutions
Jason Wang and Michael West, Metara
- Nanotechnology Overview
Philip Wong, Stanford
- Small Angle X-ray Scattering Metrology for Sidewall Angle and Cross Section of Nanometer Scale Line Gratings
Wen-li Wu, NIST
- MOSFET Scaling Trends, Challenges, and Potential Solutions Through the End of the Roadmap: A 2005 Perspective
Peter Zeitzoff and Howard Huff, ISMT
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