The Electrical Support Group consists of a staff of electrical engineers, engineering assistants, and technicians, who design and construct electronic instrumentation for high energy physics experiments.  In general, we provide electronics support for the programmatic activities of the division.  In recent years, we have designed and built instrumentation for many high energy physics experiments world-wide, including:

ATLAS      (CERN, in Geneva, Switzerland)

 CDF          (Fermilab, in Batavia, Illinois)

 MINOS     (Fermilab)

 ZEUS        (DESY, in Hamburg, Germany)

 Soudan 2   (Soudan Mine, Ely Minnesota)

We are skilled in many areas of electronics instrumentation, and have three areas of specialization:

 

1.  High-Speed Data Processors Types of Projects: Data Acquisition Trigger Processors Communication Interfaces   Implementation Techniques: Printed Circuit Board Design Programmable Logic Devices (PLD) Field Programmable Gate Arrays (FPGA) Surface Mount Technology Ball Grid Arrays (BGA)

2.  Front End Electronics Types of Projects: Charge Amplifiers Preamplifiers Digitizers Discriminators Implementation of Custom Circuits (ASICS) Noise Measurement, Analysis, & Abatement;  Grounding & Shielding HV Power Supply Design   Implementation Techniques: Printed Circuit Board Design Surface Mount Technology Custom Circuit Design (with Fermilab) Bare Die or Chip on Board (COB) Printed Circuit Board Design

3.  System Design Types of Projects: Trigger Systems (CDF, ATLAS, ZEUS) Front End System for Shower Max (CDF) Front End System for Calorimetry (MINOS) Front End System for Tracking (ZEUS)     Leadership Roles: Project Engineer for CDF Shower Max Sytem Level 3 Manager for MINOS Near Detector Front End Electronics

 

We Are A Prolific Group, with a Dedicated, Professional Staff

We Actively Pursue New Projects, and Take on Leadership Roles in Electronics

We Actively Pursue New Technologies and Design Methodologies

 

The Electronic Support Group is a Major Resource for ANL HEP, and Also US HEP

We Contribute to HEP Experiments World-Wide

 

For a List and Summary of our Staff, Click  HERE

For Technical Information on Our Projects, Click  HERE

To Go Back the ANL HEP Division Web Page, Click  HERE

ATLAS Level 2 Trigger Region of Interest (ROI) Builder Receives Information from Level 1 Trigger  Forms a “Record,” and Passes it to the Trigger Supervisor for Level 2 Trigger Processing  Operates at 100 KHz Maximum Output Trigger Rate High Speed, High Bandwidth, High Density Design  Status:  1st Prototype Built & Tested at CERN;  Design of Final Prototype in Progress   Schedule:  Production ~2004 Extensive Use of High-Density        Programmable Logic For Technical Information, Click  HERE

ATLAS Communication Link TTC Mezzanine Card Interface for Timing and Control Information from Master Clock (TTC), Transmitted Serially over Fiber to All Parts of Detector Hosts TTCrx Custom Chip, Developed at CERN  High Speed, High Bandwidth, High Density Design  Uses Ball Grid Array (BGA) Technology  Status:  4 Prototypes Tested in ATLAS Tilecal Testbeam;  Other Testing in Progress  Schedule:  Production ~2004 High Density Programmable Logic,        BGA Packaging

ATLAS Communication Link Gigabit Ethernet Link Source Card Receives “S-Link” Input Data Streams from Front-End Electronics  Buffers Data, & Re-Transmits over Gigabit Ethernet Fiber to Trigger Used to Send Information to ROI Builder  High Speed, High Bandwidth, High Density  Status:  Prototypes Built;  Testing in Progress at CERN  Schedule:  Production ~2004 Extensive Use of High Density        Programmable Logic,         Complex Functionality

CDF Shower Max SMXR Data Processor Receives Data Streams from Front-End Electronics, Provides Buffering for Read-Out By Higher-Level Processors High-Speed, High-Bandwidth Operation 9U x 400mm VME Board  100 Boards Built for Production Status:  Production Completed Spring, 2001, Installed & Working on Detector   Extensive Use of High Density            Programmable Logic,             Complex Functionality For Technical Information, Click  HERE

CDF Shower Max SQUID - Front End Electronics Receives & Processes Charge Signals from Shower Max Detectors (Multi-Anode Phototubes and Wire Chambers) Digitizes & Buffers Signals for Read-Out 16 Bit, Deadtimeless Operation at 7.5 MHz Uses SMQIE ASIC, A Custom Chip Designed at Fermilab SIMM Module Construction, 4 Channels/Card  6000 Boards Built for Production Status:  Production Completed Spring, 2001, Installed & Working on Detector   Low Noise, High Precision, Mixed            Mode Operation, Implementation             of a Custom Chip

CDF Shower Max CES Preamp - Front End Electronics Receives & Processes Charge Signals from CES Shower Max Detector (Wire Chambers in Central Detector) Differential Input, 120 Ohm Input X50 Gain, Current Drive Output SIP Construction, Surface Mount Parts 12,000 Boards Built for Production Status:  Production Completed Spring, 2001, Installed & Working on Detector   Low Noise, High Precision Operation

CDF Level 2 Trigger RECES - Shower Max Trigger Receives Information from Electronics for Central Electromagnetic Shower Detector (CES) in Central Barrel Used to Trigger on Electrons & Photons  Passes Information to the Level 2 Trigger Processor  Operates at 100 KHz Maximum Output Trigger Rate 9U VME AUX Board for CDF MAGIC Bus Crates High Speed, High Bandwidth, High Density Design  6 Boards Built for Production Status:  Production Completed Spring, 2001, Installed & Working in Trigger System Extensive Use of High-Density        Programmable Logic For Technical Information, Click  HERE

MINOS Near Detector Electronics MASTER Data Processor Receives Data Streams from Front-End Electronics, Provides Buffering for Read-Out By Higher-Level Processors High-Speed, High-Bandwidth Operation 9U x 400mm VME Board  100 Boards Built for Production Status:  Production in Progress, Complete by Dec. 2003   Extensive Use of High Density            Programmable Logic,             Complex Functionality For Technical Information, Click  HERE

MINOS Near Detector Electronics MINDER - Front End Electronics Receives & Processes Charge Signals from Near Detector Calorimeter (Multi-Anode Phototubes with Scintillator) Digitizes & Buffers Signals for Read-Out 16 Bit Operation at 53 MHz Uses QIE7 ASIC, A Custom Chip Designed at Fermilab Hosts 16 MENU Modules (SIMMs Designed at Fermilab that Host the Custom Chips) 650 Boards Built for Production Status:  Production in Progress, Complete by Dec. 2003   Low Noise, High Precision, Mixed            Mode Operation, Implementation             of a Custom Chip For Technical Information, Click  HERE

ZEUS Straw Tube Tracker Main Board - Front End Electronics Receives & Discriminates Charge Signals from Straw Tube Tracker  Front End Board Resides on Detector, and Hosts the ASDQ, A Custom Front End Chip Designed at PENN Low-Noise, High Sensitivity (2 fC)  150 Boards for Production Status:  Completed Spring, 2001, Installed & Working on Detector   High-Density Layout, Low Noise,            Mixed Mode Operation,             Implementation of a Custom Chip For Technical Information, Click  HERE

ZEUS Straw Tube Tracker Driver Board Receives Discriminated Signals from Main Board Drives Signals ~42 M from Detector to Counting Room Contains 16 Driver Amplifiers Configured as SIPs Compensates for Lossy Cable to Achieve Good Timing Resolution (Tr ~ 5 nS) 150 Boards for Production Designed at ANL, Produced by Tel Aviv Univ. Status:  Completed Spring, 2001, Installed & Working on Detector   Novel Amplifier for Compensating            Lossy Cable For Technical Information, Click  HERE

ZEUS Barrell Calorimeter Cockroft-Walton Phototube Base PMT Base with Internal High Voltage Generation from Low Voltage DC Low Power, Low-Noise, with Monitor Read Back Replacement for Existing Failing Bases 500 (1000) Boards for Production Designed at ANL, produced by Penn State Univ. Status:  Production of 500 Completed in Spring, 2001, Production of Additional Bases in Progress    Low Noise, High Density,             Unique Packaging, Reliability