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QCDOC Computing

at Brookhaven National Laboratory

BNL hosts two 12,288 nodes (10+ TeraFlops) QCDOC machines: one for the RBRC community funded by the RIKEN laboratory and one for the US Lattice Gauge Theory community funded by the US Department of Energy. A third QCDOC machine for the UKQCD collaboration is located in Edinburgh, Scotland and is funded by PPARC.

The QCDOC (QCD On a Chip) architecture has been designed to provide a highly cost-effective, massively parallel computer capably of focusing significant computing resources on relatively small but extremely demanding problems. The individual processing nodes are PowerPC-based and interconnected in a six-dimensional, low-latency mesh network with the topology of a torus. Each node, designed by our collaboration and built by IBM, includes a single custom ASIC plus DDR SDRAM. It has a peak speed of 1 Gigaflops. More information about this architecture can be found on the following QCDOC architecture and recent publication web pages.

QCDOC design is a natural evolution of that used in our earlier QCDSP machines (Quantum Chromodynamics on Digital Signal Processors). QCDSP incorporated a low-latency four-dimensional mesh network to realize peak speeds of 1 Teraflops with 20,000 nodes. QCDSP won the Gordon Bell prize at Supercomputing 98 and was acknowledged as the world’s fastest non-commercial supercomputer. A separate evolution of the regular mesh architecture of QCDSP is represented by IBM’s Blue Gene/L supercomputer, which uses a three-dimensional mesh, will incorporate up to 64,000 processing nodes and has a peak speed of 360 Teraflops.

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QCD On a Chip

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Ed McFadden and Joe DePace show off a QCDOC mother board which holds 64 nodes as a 26 hypercube which breaks down to 32 physical Daughter Boards. Each QCDOC daughter board holds two nodes and their associated DIMMs.

More information:

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Last Modified: September 3, 2008