This class provides for process or apparatus for detecting
and correcting errors in electrical pulse or pulse coded data.
This class also provides for process or apparatus for detecting
and recovering from faults in electrical computers and digital data
processing systems, as well as logic level based systems.
Electricity: Measuring and Testing, appropriate subclasses for process and apparatus
for measuring, testing or sensing of electric properties or measuring,
testing or sensing of nonelectric properties by electric means.
Coded data Generation or Conversion, appropriate subclasses for process and apparatus
utilizing electrical pulse coding techniques without error correcting/detecting
functions for the generating or conversion of coded data.
Facsimile and Static Presentation Processing, appropriate subclasses for process and apparatus
for testing and performance monitoring of facsimile devices.
Static Information Storage and Retrieval,
subclass 200 and 201, for process and apparatus including the
specifics of memory devices which are tested for defects or erroneous
information.
Data Processing: Artificial Intelligence,
subclasses 1+ for fuzzy logic, subclasses 15+ for neural
networks and subclasses 45+ for knowledge processing systems.
Electrical Computers and Digital Processing Systems:
Multicomputer Data Transferring or Plural Processor Synchronization, appropriate subclasses for multiple computer or
computer process systems.
Electrical Computers and Digital Data Processing
Systems: Input/Output, appropriate subclasses for process and apparatus
for computer input or output systems.
Electrical Computers and Digital Processing Systems:
Memory,
subclasses 133+ for entry replacement strategies and page fault
recovery, and subclasses 161+ for data archiving.
Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing(e.g., processors), appropriate subclasses for process and apparatus
for computer structure and program execution systems.
Electrical Computers and Digital Processing Systems:
Support, appropriate subclasses for process and apparatus
for computer cases, housing and supports.
Information Security,
subclasses 1 through 36for information security in computers or digital processing
system.
SECTION III - GLOSSARY
BUS
A conductor used for transferring data, signals or power.
COMPUTER
A machine that inputs data, processes data, stores data, and
outputs data.
DATA
Representation of information in a coded manner suitable
for communication, interpretation, or processing.
ADDRESS DATA
Data that represent or identify a source or destination.
INSTRUCTION DATA
Data that represent an operation and identify its operands,
if any.
STATUS DATA
Data that represent conditions of data, digital data
processing systems, computers, peripherals, memory, etc.
USER DATA
Data other than address data, instruction data, or status data.
DATA PROCESSING
See PROCESSING, below.
DIGITAL DATA PROCESSING SYSTEM
An arrangement of processor(s) in combination with either
memory or peripherals, or both, performing data processing.
ERROR
Manifestation of a fault as an undesired event that occurs
when actual behavior deviates from the behavior that is required
by initial specification. This includes a change in information
content of pulse or pulse coded data to a state or value other than
the normal state or value of a properly operating device or system.
FAULT
A flaw in a functional unit (hardware or software).
INFORMATION
Meaning that a human being assigns to data by means of the
conventions applied to that data.
MEMORY
A functional unit to which data can be stored and from which
data can be retrieved.
PERIPHERAL
A functional unit that transmits data to or receives
data from a computer to which it is coupled.
PROCESSING
Methods or apparatus performing systematic operations upon
data or information exemplified by functions such as data or information
transferring, merging, sorting, and computing (i.e., arithmetic
operations or logical operations).
(1)
Note. In this class, the glossary term data is used to modify
processing in the term data processing; whereas the term digital
data processing system refers to a machine performing data processing.
PROCESSOR
A functional unit that interprets and executes instruction data.
RECOVERY
Responding to a fault in a system by either returning
a system to a previous level of correct operation, achieving a degraded
level of correct operation, or safely shutting down the system.
SECURITY
Extent of protection for system hardware, software, or data
from maliciously caused destruction, unauthorized modification,
or unauthorized disclosure.
This subclass is indented under subclass 100. Subject matter further including means or steps for increasing
a probability of correctly performing services (e.g., data processing) throughout
a time interval, given correct performance at the beginning of the
interval, or for increasing the probability of correctly performing
services at any given instant.
(1)
Note. Reliability features in a data processing control system
are classified elsewhere.
Cryptography,
subclass 4 for stored digital data access or copy prevention in
combination with data encryption; e.g., software program protection
or computer virus detection in combination with data encryption.
Data Processing: Generic Control Systems or Specific
Applications,
subclasses 79 through 82for reliability features in a data processing generic
control system.
This subclass is indented under subclass 1. Subject matter further including means or steps for responding
to a failure by either returning a system to a previous level of
correct operation, achieving a degraded level of correct operation,
or safely shutting down the system after detecting the error or
locating the fault.
(1)
Note. Classification here requires significant data processing
features claimed. For fault recovery in a system without significant
data processing method or apparatus, classification is elsewhere. See
the SEE OR SEARCH THIS CLASS, SUBCLASS and SEE OR SEARCH CLASS
notes below.
(2)
Note. Classification here requires notification or detection
of the fault, its location, and a further action. Subcombinations
used in the process of fault recovery; e.g., fault locating, are classified
below.
(3)
Note. "Page faults" are a species of faults peculiar to memory
accessing and are classified elsewhere in this class. See the SEE
OR SEARCH THIS CLASS, SUBCLASS notes below.
This subclass is indented under subclass 2. Subject matter further including means or steps for recovery
by selecting a correct output from a concurrently active redundant
functional unit in place of the output of the failed functional unit,
or by replacing or isolating the failed functional unit.
(1)
Note. This subclass is for fault recovery by masking or reconfiguration
in combination with significant data processing. Generic fault recovery
is classified elsewhere. See the SEE OR SEARCH CLASS notes below.
This subclass is indented under subclass 3. Subject matter further including means or steps for recovery
at a network level (e.g., recovery from nodal failures).
Communications: Electrical, various subclasses for residual electrical communication
systems,
subclass 2.23 for alternate routing in a plural stage communication
system, and see related Class 342 and Class 343.
Communications: Directive Radio Wave Systems
and Devices (e.g., Radar, Radio Navigation), various subclasses for alternate routing in a plural
stage radar network.
Multiplex Communications,
subclasses 216+ for fault recovery and subclasses 229+ for
data flow congestion prevention and control in a multiplex communication
system.
This subclass is indented under subclass 3. Subject matter further including means or steps for recovery
from a fault of a memory function level or the peripheral function
level, or for recovery limited to a specialized processor accessing
either memory, peripheral, or other I/O device.
(1)
Note. "Page faults" are a species of faults peculiar to memory
accessing and are classified elsewhere. See the SEE OR SEARCH THIS
CLASS, SUBCLASS notes below.
Electrical Computers and Digital Data Processing
Systems: Input/Output,
subclasses 1+ , for transferring data from one or more peripherals
to one or more computers for the latter to process, store, or further
transfer or for transferring data from the computers to the peripherals
(i.e., Input/Output data processing).
Electrical Computers and Digital Processing Systems:
Memory,
subclasses 100+ for means (e.g., processor, controller, etc.) or
steps for governing memory in a digital data processing system or
the passage (e.g., reading or writing) of data thereto and subclasses
133+for entry replacement strategies and page fault recovery.
This subclass is indented under subclass 5. Subject matter further including means or steps for recovery
by accessing redundant stored data.
(1)
Note. This and indented subclasses rely on information which
is a function of the actual data of concern as exemplified in one
simple form by parity data. The species of fault recovery or avoidance
concerned with storing archival verbatim copies of data is classified
elsewhere. See SEE OR SEARCH CLASS notes below.
(2)
Note. Parity and error-correction coded storage of general
utility in a system without data processing features claimed are
classified elsewhere in this class. See SEE OR SEARCH THIS CLASS,
SUBCLASS notes below.
Electrical Computers and Digital Processing Systems:
Memory,
subclasses 161+ for preventing the corruption, loss, alteration,
or disclosure of data by storing, as in making backup copies.
This subclass is indented under subclass 6. Subject matter further including means or steps for statically
replacing a failed memory component.
(1)
Note. Classification here requires more than selecting a correct
output from a concurrently active redundant functional unit in place
of the output of the failed component.
This subclass is indented under subclass 5. Subject matter further including means or steps for recovery
by disabling access to a failed memory location.
(1)
Note. Classification here requires more than selecting a correct
output from a concurrently active redundant functional unit in place
of the output of the failed component.
This subclass is indented under subclass 5. Subject matter further including means or steps for recovery
from fault of an access processor (e.g., memory management unit
(MMU), direct memory access (DMA) processor, I/O processor,
etc.).
Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g., processors), appropriate subclasses for digital data processing
system architecture, per se.
Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g., processors), appropriate subclasses for digital data processing
system architecture, per se.
This subclass is indented under subclass 10. Subject matter further including means or steps for recovery
employing redundant processors substantially simultaneously performing
the same operation.
Data Processing: Generic Control Systems or Specific
Applications,
subclass 3 for master/slave processors in a data
processing generic control system, and subclasses 79-82 for protection
or reliability in a digital data processing control system.
This subclass is indented under subclass 11. Subject matter further including means or steps for maintaining
processor state synchronization to achieve redundancy of operation.
(1)
Note. Classification here requires a redundant processor for
the purpose of reliability, such as by consideration of state of
internal registers and the like of the redundant processors and
thus the machines themselves. Synchronization in the form of
timing and clock skew is classified elsewhere. See the SEE OR SEARCH
THIS CLASS, SUBCLASS notes below.
(2)
Note. Classification here requires the existence of a fault
condition. Synchronization maintenance at the clock level, however,
is classified elsewhere. See the search class notes below.
Electrical Computers and Digital Processing Systems:
Multicomputer Data Transferring or Plural Processor Synchronization, appropriate subclasses for multicomputer and synchronizing,
and for synchronization maintenance of plural processors, per se.
Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g., processors), appropriate subclasses for task management, per
se.
Electrical Computers and Digital Processing Systems:
Support,
subclasses 400+ , for clock synchronization, per se, subclasses
500+, for digital data processing system clock, pulse and timing
interval generation, per se.
This subclass is indented under subclass 10. Subject matter further including means or steps for readying
a backup processor or digital data processing system to replace
a failed primary processor or digital data processing system, or to
receive recent processing result(s) from a backup processor or digital
data processing system that may be relied upon.
(1)
Note. Classification here allows for the backup processor
or digital data processing system to be performing operations unrelated
to backup operation before or after failure of the primary processor
or digital data processing systems.
Data Processing: Generic Control Systems or Specific
Applications,
subclasses 2 through 7for data processing control system applications employing
plural processors, and subclasses 79-82 for protection or reliability
in a digital data processing system based control system .
This subclass is indented under subclass 3. Subject matter further including means or steps for recovery
using power supply subsystem component redundancy.
Electrical Computers and Digital Processing Systems:
Support,
subclasses 300+ , for power control in a digital data processing
system environment, and subclass 321 for electrical digital calculating
computer (i.e., calculator) with power saving feature.
This subclass is indented under subclass 2. Subject matter further including means or steps for recovery
by restoring data in a data file, or data for a process, to data
at a previous point in time.
(1)
Note. The species of fault recovery or avoidance concerned
with storing verbatim copies of data is classified elsewhere. See
the SEE OR SEARCH THIS CLASS, SUBCLASS notes below.
(2)
Note. Parity and error-correction coded storage of general
utility in a system without data processing features claimed is
classified elsewhere.
(3)
Note. This state recovery subclass provides for reliability
and availability recovery under the condition of a fault. Data management,
per se, is classified elsewhere. See the search class notes below.
Electrical Computers and Digital Processing Systems:
Memory,
subclasses 141+ for cache memory coherency, per se; subclasses
147+ for shared memory data processing which may employ
data management principles; and subclasses 161+ for preventing
the corruption, loss, alteration, or disclosure of data by storing, as
in making backup copies.
Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g., processors),
appropriate subclasses for source code management and software version
management.
This subclass is indented under subclass 15. Subject matter further including means or steps for recovery
by re-executing an operation in response to detecting an error in
an operation.
(1)
Note. Recovery by operation retry or error detection by sequential
repetition in a system without data processing features is classified
elsewhere.
This subclass is indented under subclass 15. Subject matter further including means or steps for recovery
of a communication process (e.g., a session) using a record.
Electrical Computers and Digital Data Processing
Systems: Input/Output, appropriate subclasses for I/O processing
and communication between computers and peripherals.
This subclass is indented under subclass 15. Subject matter further including means or steps for recovery
of data in the presence of uncommitted action using a record of
the data created before the action.
Data Processing: Database and File Management
or Data Structures,
subclasses 200 through 206for database and file maintenance in the absence
of a fault condition.
Data Processing: Presentation Processing of Document,
Operator Interface Processing, and Screen Saver Display Processing, appropriate subclasses for a word data processing application
on computer, particularly
subclasses 255 through 272for editing in a text data processing application.
This subclass is indented under subclass 15. Subject matter further including means or steps for recovery
using sets of sequenced or linked recovery data containing set sequencing
or linking data.
This subclass is indented under subclass 15. Subject matter further including means or steps wherein
recovery is controlled by verifying the accuracy of the state data.
This subclass is indented under subclass 15. Subject matter further including means or steps wherein
recovery is controlled by a power supply status monitor.
Electrical Computers and Digital Processing Systems:
Support,
subclass 321 for electrical digital calculating computer (i.e.,
calculator) with power saving feature, and subclass 340, for generic
power control monitoring in a digital data processing system environment.
This subclass is indented under subclass 2. Subject matter further including means or steps for recovery
using clearing or initializing of a processor register.
This subclass is indented under subclass 2. Subject matter further including means or steps for recovery
including termination of a system component to a safe condition.
(1)
Note. Isolating (i.e., disabling) an output of a failed network,
processor, memory, peripheral, I/O, or power supply component
is classified elsewhere. See SEE OR SEARCH THIS CLASS, SUBCLASS notes
below.
This subclass is indented under subclass 1. Subject matter further including means or steps for pinpointing
a fault using either a reactive diagnosing or a proactive testing,
including testing for developmental stage fault avoidance, for assurance,
or for maintenance.
(1)
Note. An invention directed to locating a fault in a digital
data processing system including more than nominal data processing,
or where the fault is specific to a nongeneral use of a digital
data processing system, is classified here. fault locating in combination
with a specific art device not of the basic subject matter of this
class is classified with the art device.
This subclass is indented under subclass 25. Subject matter wherein the testing is performed using an
artificial intelligence technique; e.g., fault tree, reasoning rules,
self-learning.
This subclass is indented under subclass 25. Subject matter further including means or steps related
to an access structure specialized for observing or controlling
a test or diagnosis.
This subclass is indented under subclass 27. Subject matter further including means or steps for using
a tester component that can emulate (i.e., functionally operate
as) a normal component in the tested system.
This subclass is indented under subclass 28. Subject matter further including means or steps for using
memory that can functionally replace a system component.
(1)
Note. For classification here the replaced component need
not be a memory.
Data Processing: Structural Design, Modeling,
Simulation, and Emulation, appropriate subclasses for general purpose simulation
or emulation of system components.
This subclass is indented under subclass 27. Subject matter further including means or steps for testing
or diagnostic access using specialized testing or diagnosing hardware
permanently built into a component of the system being tested or
diagnosed.
This subclass is indented under subclass 27. Subject matter further including an additional processor
for controlling all or part of in-system testing or diagnosis.
This subclass is indented under subclass 25. Subject matter further including means or steps for selection
or generation of a signal (i.e., data) for testing or diagnosing.
This subclass is indented under subclass 32. Subject matter further including means or steps for deriving
a test or diagnosis program based on an analysis of specification,
design, or output of the system to be tested or diagnosed.
Data Processing: Structural Design, Modeling,
Simulation, and Emulation,
subclasses 13 through 22for simulating electronic device and electrical
system.
Data Processing: Design and Analysis of Circuit
or Semiconductor Mask, appropriate subclasses for designing and analyzing
circuit or semiconductor mask.
This subclass is indented under subclass 32. Subject matter further including means or steps for controlling
a processor or digital data processing system to be tested or diagnosed
by applying an interrupt, halt, or clock signal to a processor or
digital data processing system.
Electrical Computers and Digital Processing Systems:
Memory,
subclass 204 for virtual address branch or jump address predicting;
and subclasses 213 for generalized prefetch, look-ahead, jump, or
predictive address generating.
Electrical Computers and Digital Processing Systems:
Processing Architecture and Instruction Processing (e.g., Processors),
subclass 227 , for instruction processing in support of testing,
debugging, emulation, etc.
This subclass is indented under subclass 32. Subject matter further including means or steps for substituting
or adding a testing or diagnosing instruction into a program or
instruction data stream of a processor or digital data processing
system being tested or diagnosed.
Electrical Computers and Digital Processing Systems:
Processing Architecture and Instruction Processing (e.g., Processors), appropriate subclasses for instruction processing, per se,
including instruction alignment, fetching and decoding, and for
processing control at the processor level, per se, particularly
subclass 227 , for instruction processing in support of testing,
debugging, emulation, etc.
This subclass is indented under subclass 32. Subject matter further including means or steps for performing
a sequence of tests automatically in response to a power-up or initialization action.
Electrical Computers and Digital Data Processing
Systems: Input/Output, appropriate subclasses, for assigning operating characteristics
to peripherals, particularly
subclass 104 , for utilizing a hardware structure for providing
a processor with an arrangement of the digital data processing system including
characteristics of the digital data processing system’s
components.
Electrical Computers and Digital Processing Systems:
Memory,
subclass 170 for automatically determining and allocating memory
space or specifying an allocation.
Electrical Computers and Digital Processing Systems:
Support,
subclasses 1 through 100,for digital data processing system initialization
and configuration at boot-time.
This subclass is indented under subclass 25. Subject matter further including means or steps for evaluating
the output, state, or design, of a computer system or a processor
or a program, for fault locating.
Data Processing: Structural Design, Modeling,
Simulation, and Emulation,
subclasses 13 through 22for the use of database in simulating electronic
device and electrical system.
Data Processing: Design and Analysis of Circuit
or Semiconductor Mask, appropriate subclasses for designing and analyzing
circuit or semiconductor mask.
This subclass is indented under subclass 37. Subject matter further including means or steps for locating
a fault in software or testing software.
(1)
Note. This subclass also provides for detecting an error in
instruction data in combination with a digital data processing system.
Generic coded information error detection is classified elsewhere. See
SEARCH CLASS notes below.
(2)
Note. This subclass also provides for fault locating in software
analysis by mechanisms such as debugging, automatic code generating,
object oriented design, etc.
This subclass is indented under subclass 37. Subject matter further including means or steps for locating
a fault by using a monitor for classifying or otherwise recognizing
a sequence of events.
Electrical Computers and Digital Processing Systems:
Multicomputer Data Transferring or Plural Processor Synchronization,
subclass 224 for computer network managing including monitoring.
This subclass is indented under subclass 25. Subject matter further including means or steps for fault
locating that are specific to a device under test.
This subclass is indented under subclass 40. Subject matter further including means or steps for fault
locating specific to fault in a reliability enhancing component.
This subclass is indented under subclass 40. Subject matter further including means or steps for fault
locating specific to a fault in a bus, peripheral or I/O
channel, or network path.
Electrical Computers and Digital Data Processing
Systems: Input/Output,
subclasses 100+ , for subject matter directed to system intraconnecting and
bus access processing.
This subclass is indented under subclass 40. Subject matter further including means or steps for fault
locating specific to a fault in a peripheral device.
Electrical Computers and Digital Data Processing
Systems: Input/Output, appropriate subclasses, for subject matter directed
to Input/Output processing and communication between peripherals
and computers or digital data processing systems.
This subclass is indented under subclass 25. Subject matter further including means or steps for recording
output from the system under test or diagnosis.
This subclass is indented under subclass 1. Subject matter further including means or steps for monitoring
event duration and event counts for anticipating or recognizing
faults.
(1)
Note. This subclass relates to the fault avoidance species
of reliability.
(2)
Note. This subclass includes event duration and counting arrangements
for statistical analysis of system operations and predictive methods
of fault avoidance.
Electrical Pulse Counters, Pulse Dividers, or
Shift Registers: Circuits and Systems,
subclasses 64+ for shift registers, and subclasses 107+ and 11+ for
counters.
Electrical Computers: Arithmetic Processing and
Calculating,
subclasses 200+ for various arithmetic data processing operations
performed by digital calculating computers.
Electrical Computers and Digital Processing Systems:
Multicomputer Data Transferring or Plural Processor Synchronization,
subclass 224, for computer network managing including monitoring.
This subclass is indented under subclass 1. Subject matter further including means or steps for automated
on-line sensing of errors, or for storing or propagating such error
information (e.g., error logging).
This subclass is indented under subclass 48. Subject matter further including means or steps for detecting
an error based on the information content of an instruction, a message,
or data.
This subclass is indented under subclass 49. Subject matter wherein an ordering of state information
related to a succession of data, instructions etc., is the basis
for state analysis.
Electrical Computers and Digital Processing Systems:
Memory,
subclass 204 for virtual address branch or jump address predicting;
and subclass 213 for generalized prefetch, look-ahead, jump, or
predictive address generating.
Electrical Computers and Digital Processing Systems:
Processing Architecture and Instruction Processing (e.g., Processors), appropriate subclasses for instruction fetching
and prefetching and for branching instruction processing and for
task management and control, per se.
This subclass is indented under subclass 50. Subject matter for detecting consistency of information
by using a code (e.g., parity, etc.) which is generated from the
information.
(1)
Note. Error checking codes are a function of the actual data
of concern, as exemplified in one simple form by parity data.
Electrical Computers and Digital Processing Systems:
Memory,
subclasses 161+ for preventing the corruption, loss, alteration,
or disclosure of data by storing, as in making backup copies.
Electrical Computers and Digital Processing Systems:
Memory,
subclass 144 for cache status data bits (e.g., bits indicating
modified, valid, dirty data), wherein coherency for each unit or
block of data includes associated identifier bit(s) to indicate
the validity status of an associated cached location; subclass 156
for status storage control techniques including provisions for storing
status data (e.g., control status words, program status words, etc.)
associated with memory accessing and control; and subclass 165 for
movement/transfers of data amongst locations within a same memory
level.
Electrical Computers and Digital Processing Systems:
Support,
subclass 375 for synchronization maintenance of plural processors,
subclasses 400-401 for clock synchronization, per se, and subclasses
500-503 for digital data processing system clock, pulse and timing
interval generation, per se.
Electrical Computers and Digital Processing Systems:
Virtual Machine Task or Process Management or Task Management/Control,
subclass 1 for virtual machine task or process management
and 100-108 for task management or control, in general.
This subclass is indented under subclass 55. Subject matter further including means or steps for detecting
errors related to a flaw in a bus, peripheral, or I/O channel
device.
This subclass is indented under subclass 48. Subject matter further including means or steps for propagating
error information so as to make notification of detected error.
This subclass is indented under the class definition. Subject matter for enhancing the ability of a system,
which is programmed for organization or manipulation of data, to
respond to an unexpected hardware or software failure.
(1)
Note. Classification herein requires more than nominal recitation
of data processing components in combination with means or steps
for furthering correct data processing operations by mechanisms including
error detecting, performance monitoring, fault locating, and fault recovery.
(2)
Note. The species of reliability and availability directed
to memory accessing and control with data archiving, backups, device
access limiting, and security are classified elsewhere, see the SEE
OR SEARCH CLASS notes below, other species of reliability and availability
in memory accessing and control such as isolating failed memory
and storing redundant data are classified herein.
Cryptography,
subclasses 3+ for stored information access or copy prevention
(e.g., software program protection or computer virus protection) in
combination with data encryption, and subclasses 22 - 25 and 50
for electric signal modification and other appropriate subclasses.
This subclass is indented under the class definition. Subject matter further including means or steps for detecting
and/or correcting errors in electrical pulse or pulse coded
data, in addition, electrical based systems or devices which utilize
techniques for detecting an error or fault condition, without recitation
of specific data processing system components, are classified herein,
said techniques include testing and diagnosis at the logic/component
level.
(1)
Note. Fault detection herein excludes processes and apparatus
wherein there is no actual testing using digital data containing
intelligence.
(2)
Note. This class does not include detecting the distortion
or degradation of pulse coded data per se, but rather includes detecting
and/or correcting of errors in the information content
of pulse or pulse coded data which may have occurred due to distortion
or degradation of the coded data, thereby changing the state or value
of the information content to such an extent as to comprise an error
by definition.
(3)
Note. Nominally recited art devices or systems external to
this class, claimed in combination with subject matter under the
class definition, are classified in this class, for example, static
memory devices claimed in combination with error correcting encoding/decoding apparatus
are classified herein, and a nominally recited telecommunications switching
system claimed in combination with fault diagnostic and/or
recovery apparatus would also be classified herein.
(4)
Note. Significantly claimed apparatus external to this class
claimed in combination with apparatus under the classdefinition,
which perform fault detection/correction techniques, are
classified with the external apparatus, for example, a significantly
claimed multiplex communication apparatus that performs general testing
of its components would be found elsewhere, see SEE OR SEARCH CLASS
below.
Coded Data Generation or Conversion, various subclasses for systems related to generic
systems for either (a) originating or emitting a coded set of discrete
signals or (b) translating one code into another code wherein the
information signal content remains the same but the formats may differ.
Facsimile and Static Presentation Processing,
subclasses 406 and 504 for systems where a facsimile apparatus is
monitored, measured, calibrated, or tested.
Multiplex Communications,
subclasses 13+ and 100+ for subject matter wherein part
of a multiplex system is monitored and tested to evaluate its performance,
including circuit continuity checking, repeater testing, loopback
testing, and alternate routing due to failure.
This subclass is indented under subclass 699. Subject matter in which an error caused by the time delay
between plural parallel bits forming a byte or data word is detected
or corrected.
This subclass is indented under the class definition. Subject matter in which a change in data format or sequence
is utilized to improve the error detection/correction capability
of a coding scheme.
This subclass is indented under subclass 701. Subject matter which changes the format of digital data
by having the signal with the data written into or read out of a
storage device.
(1)
Note. Address permutation arrangements are included in this
subclass.
This subclass is indented under the class definition. lSubject matter in which the proper operation of the error
detection/correction or fault detection/recovery
apparatus itself is verified.
This subclass is indented under the class definition. Subject matter which determines the number of bits in error
or the number of bits in error per unit of time.
This subclass is indented under subclass 704. Subject matter having a main data path and a secondary data
path having intentionally degraded performance connected in parallel, the
secondary path having a decision device to compare and evaluate
the disagreement between the paths.
(1)
Note. Each disagreement is called a pseudo-error.
This subclass is indented under subclass 704. Subject matter including an reversible accumulating register
which counts up in response to an error and counts down in response
to an error-free increment of time.
This subclass is indented under subclass 704. Subject matter in which a determination of the error rate
is used to control synchronization between devices.
This subclass is indented under subclass 704. Subject matter including control of system operation by
either deactivation of the system, or controls a parameter related
to normal system operation, in response to error count or error
rate.
This subclass is indented under subclass 699. Subject matter in which the information bearing parameter
(amplitude, pulse position, etc.) of a data pulse is evaluated to
determine the proper logic state or value.
(1)
Note. Subject matter in this subclass relates to determining
if a data pulse represents a particular given logic state, e.g.,
logic one as opposed to logic zero.
This subclass is indented under subclass 699. Subject matter in which the spare apparatus comprises only
a location, or a contiguous group of locations of memory.
This subclass is indented under subclass 699. Subject matter in which the diagnostic testing is performed
upon a channel of a transmission medium with a device for supplying
digital data thereto.
(1)
Note. The transmission facility includes the transmission
medium and all associated equipment required to transmit a message.
This subclass is indented under subclass 712. Subject matter in which the transmission facility is tested
by applying a test pattern to the device under test and comparing
the output to a reference test pattern.
This subclass is indented under subclass 715. Subject matter in which the transmission facility is configured
so that the receiver shunts the test pattern back to transmitter
for comparison at the transmitter.
This subclass is indented under subclass 712. Subject matter in which a plurality of transmission stations
or devices are configured in a serial fashion to form a loop or
ring.
Static Information Storage and Retrieval,
subclass 200 a bad bit memory used to store information; and
subclass 201 for specifics of a memory which is tested but doesn"t include
data processing techniques.
Television Signal Processing for Dynamic Recording
or Reproducing,
subclasses 2+ and 47+ for drop-out detection or correction,
subclasses 13+ and 85+ for time correction, and subclasses
21+ and 113+ for recorder or reproducer fault
condition compensation.
This subclass is indented under subclass 718. Subject matter in which the testing is done by reading in
a test pattern, reading out the contents of the memory and comparing
the output with the test pattern read in.
This subclass is indented under subclass 719. Subject matter in which the test patterns are selected to
exercise the memory by transferring a combination of logic zeroes
and ones through the memory, e.g., alternating zeroes and ones-checkerboard
pattern.
This subclass is indented under subclass 718. Subject matter in which the diagnostic test measures an
electrical parameter of the memory device, e.g., threshold voltage.
This subclass is indented under subclass 718. Subject matter in which the diagnostic test consists of
performing an arithmetic function, such as addition, on the contents
of the memory and comparing the results to a reference value.
This subclass is indented under subclass 718. Subject matter in which the detected error or fault is registered
or recorded to present a history for diagnostic purposes.
This subclass is indented under subclass 699. Subject matter in which the diagnostic test is performed
upon a system or element performing a binary logic operation upon
a signal having plural distinct discrete states.
(1)
Note. Testing or measuring of electrical properties are classified
elsewhere unless the testing device includes analysis of the information
content of a digital signal. Control signals are not data signals.
Electricity: Measuring and Testing, appropriate subclass, particularly
subclass 73 for measuring and testing of electrical device
parameters under controlled conditions.
Electronic Digital Logic Circuitry,
subclass 16 for electronic digital logic circuitry with test
facilitating feature and subclasses 21+ for electronic
digital logic circuitry maintaining signal integrity.
This subclass is indented under subclass 724. Subject matter for testing an array of logical elements
selectively configurable to sequentially perform various binary
logic functions.
(1)
Note. Examples of such binary logic functions are AND, OR,
NAND, NOR, and NOT.
Electricity: Measuring and Testing, appropriate subclass, particularly
subclass 73.1 for measuring and testing of electrical device
parameters under controlled conditions.
Electronic Digital Logic Circuitry,
subclass 16 for electronic digital logic circuitry with test
facilitating feature, subclasses 21+ for electronic digital logic
circuitry maintaining signal integrity, and subclasses 37+ for
a programmable or multifunctional logic array circuit, per se.
This subclass is indented under subclass 724. Subject matter in which digital logic is designed for
improved testability by including shift register latches (SRL) to
enable the configuring of the circuitry into combinational logic
form.
(1)
Note. Test data is clocked (scanned) through the combinational
logic forms and then compared to a reference.
This subclass is indented under subclass 726. Subject matter where selected components in a circuit are
each provided with one or more cells, comprising a single-bit register,
coupled to a node of a component, such as an input, output, input/output
or control node, and where said cells are serially coupled in a
single chain, usually referred to as a boundary-scan chain.
This subclass is indented under subclass 726. Subject matter where a series of digits is generated in
an unpredictable, incoherent, or arbitrary pattern.
(1)
Note. Included herein is generation of a series of digits
which simulates a random pattern.
This subclass is indented under subclass 726. Subject matter having more than one group of shift register
latches connected in series, and which groups form a plurality of
shift paths (scan paths) along which data can be transmitted.
This subclass is indented under subclass 726. Subject matter including a reference timing function or
a clock-pulse generator for causing the various parts of the device
to operate on a common time base.
This subclass is indented under subclass 724. Subject matter controlled including monitoring of controlled
conditions of execution test points or nodes within the digital
logic device and the measured output (signature) is compared to
a known good signature.
This subclass is indented under subclass 724. Subject matter in which the digital logic testing equipment
includes a selectively configurable shift register, structurally
a part of the device being tested.
(1)
Note. Some selective configurations of the shift register
include a latch, linear shift register, multiple input signature register,
and a forced reset.
(2)
Note. Included herein are built-in logic block observation
(BILBO) devices.
Electricity: Measuring and Testing, appropriate subclass, particularly
subclass 73.1 for measuring and testing of electrical device
parameters under controlled conditions.
Electrical Pulse Counters, Pulse Dividers, or
Shift Registers: Circuits and Systems,
subclasses 19+ for a shift register used for measuring or testing;
and subclass 28 for error checking or correction in a shift register
system.
This subclass is indented under subclass 724. Subject matter in which each component of the logic circuit
is tested individually while physically connected to the circuit.
(1)
Note. Generally, the test instrument is connected to nodes
of the logic circuit under test in a unique way for each component.
Electricity: Measuring and Testing, appropriate subclass, particularly
subclass 73.1 for measuring and testing of electrical device
parameters (other than by information signal content) under controlled
conditions.
This subclass is indented under subclass 724. Subject matter in which the operational condition of a system
or device is determined by comparing the system or device response
to a test signal input pattern.
This subclass is indented under subclass 724. Subject matter in which the operational condition of a system
or device is determined by comparing the system or device response
to a predetermined fault-free response.
This subclass is indented under subclass 724. Subject matter in which the operational condition and identification
of an actual or potential fault is determined by comparing the system response
to a predetermined fault dictionary or truth table.
This subclass is indented under subclass 724. Subject matter in which the specific means or method of
generating a test pattern for a digital logic testing system is
claimed.
Computer Graphics Processing and Selective Visual
Display Systems,
subclass 26 , 345, 551 for character generator in a visual
display system with selective electrical control.
Electrical Computers: Arithmetic Processing and
Calculating,
subclasses 250+ for random number generators, and subclasses 270+ for
digital function generators.
This subclass is indented under subclass 738. Subject matter where a series of digits is generated in
an unpredictable, incoherent or arbitrary pattern.
(1)
Note. Included herein is generation of a series of digits
which simulates a random pattern.
This subclass is indented under subclass 738. Subject matter including an electrical signal, the amplitude
or frequency of which varies continuously in value over time.
This subclass is indented under subclass 738. Subject matter having an electrical model or a computer
program which imitates the operation of a device under test.
Data Processing: Structural Design, Modeling,
Simulation, and Emulation,
subclasses 3 through 5for electrical analog simulator, subclasses 6-12
for simulating nonelectrical device or system, and subclasses 13-22
for simulating electronic device and electrical system.
This subclass is indented under subclass 738. Subject matter where the test pattern is applied to a distinctive
named means to carry out a special function.
(1)
Note. Examples of things that are not specific devices include
"logic device," "circuit," "device under test," etc.
(2)
Note. See sections D and E of the class definition for the
distinction between this class and classes having the specific device.
This subclass is indented under subclass 738. Subject matter including a reference timing function or
a clock pulse generator for causing the various parts of the device
to operate on a common time base.
This subclass is indented under subclass 724. Subject matter in which the device or system is tested under
controlled and varying circuit parameters, such as input voltage,
to determine the range of circuit parameter values within which
the device or system operates without error or malfunction.
This subclass is indented under the class definition. Subject matter in which the error in information content
of pulse or pulse coded data is corrected.
This subclass is indented under subclass 746. Subject matter in which a previously validated data state
or value is substituted for data state or value determined to be
erroneous.
This subclass is indented under subclass 746. Subject matter in which the digital data error correction
is achieved by retransmission of data responsive to a request.
This subclass is indented under subclass 748. Subject matter in which a retransmission of data is initiated
upon the condition that no acknowledgment (ACK) signal is returned from
the receiver.
This subclass is indented under subclass 748. Subject matter in which the digital data is returned to
the transmitter for comparison to detect an error.
This subclass is indented under subclass 748. Subject matter in which the digital data is encoded to enable
error correction at the receiver and retransmission is requested
only if the error rate exceeds the forward error correcting capability.
This subclass is indented under subclass 746. Subject matter in which a grouping of symbols (i.e., a block
of data or a data word) is transformed into a code word having an
increased number of symbols in order to provide an increased minimum
distance between code words relative to the minimum distance of
the corresponding data words in order to provide for forward correction
of the encoded data in the event that an error or erasure is subsequently
imposed on the encoded data.
(1)
Note. This subclass includes both forward error correction,
per se, (i.e., the receiver corrects the error without requiring
any further information from the sender, which requires a minimum amount
of redundancy in the transmission since not only must an error be detected,
but its location must be determined) and forward error correction
with the assistance of symbol reliability information.
(2)
Note. Forward error correction (FEC) is an error-correcting
technique that avoids the need for any reverse channel by enabling
self-correction of errors at the receiver by adding information
(at the expense of throughput) to enable the receiver to determine
what the error was and the correct information to substitute for
said error.
for convolutional codes in which each check bit
is generated as a function of a different plurality of information bits
and is interspersed among the information bits at predetermined intervals
with no natural beginning point or ending point.
This subclass is indented under subclass 752. Subject matter in which a single bit error correcting code
arrangement corrects double bit errors by successively correcting
consecutive single bit errors.
This subclass is indented under subclass 752. Subject matter including a digital data storage device having
a refresh cycle in which decaying information is read before it
becomes unrecognizable, and rewritten in original form, and decoding
a stored block data code signal for error correction during the
refresh cycle.
This subclass is indented under subclass 752. Subject matter including calculation and independent decoding
of two independent sets of check words for enhancement of error
correction.
This subclass is indented under subclass 755. Subject matter doubly encoded with Reed-Solomon codes and
interleaved to enable the correction of burst errors.
This subclass is indented under subclass 752. Subject matter which encodes digital data with both an error
correcting code (ECC) for error correction and detection, and an
additional error detection code to detect uncorrected errors.
(1)
Note. Such additional codes include a cyclic redundancy code
(CRC) and a parity bit code.
This subclass is indented under subclass 752. Subject matter having an encoder or decoder which contains
a table of all possible error patterns in a corrupted received code
word and compares the computed syndrome to these patterns to determine
the position of erroneous bits.
This subclass is indented under subclass 752. Subject matter the decoder operates upon a corrupted received
code word to compute the parity check sums which are applied to
a threshold or majority gate and an error indicated if the sums
exceed a certain value.
This subclass is indented under subclass 752. Subject matter in which the block code is capable of correcting
both random and burst errors.
(1)
Note. Random errors are of the type where each data bit is
affected independently by noise. Burst errors are of the type where
disturbances introduce errors of unspecified time duration and thus
cause a cluster of multiple consecutive data bits in error.
(2)
Note. Interlacing or interleaving techniques may be used to
give a random error correcting code the capability of correcting
both random and burst errors. A product code or concatenated code may
be formed from two codes to provide both random and burst error
correction capability.
This subclass is indented under subclass 752. Subject matter in which the block code is derived to be
most effective in correcting burst errors.
(1)
Note. An example of a block code with good burst-correcting
capability is the Reed-Solomon code. Interleaving techniques are
also utilized to improve the burst-correcting capability of a code.
This subclass is indented under subclass 752. Subject matter in which digital data being written into
or read out of a storage device is encoded in a block code format.
Dynamic Magnetic Information Storage or Retrieval,
subclasses 26 , 36.1+, 47, and 53 for error detection combined
with a magnetic, dynamic memory system.
This subclass is indented under subclass 763. Subject matter which corrects the errors upon readout of
the data and the corrected data in written into memory as a substitute
for the erroneous data.
This subclass is indented under subclass 763. Subject matter which generates a signal (pointer) upon the
occurrence of a particular type of error or failure.
(1)
Note. In many error correcting systems accessing data from
a memory or storage device, the error pointer identifies the track
or channel with which the error or failure is associated.
This subclass is indented under subclass 763. Subject matter including a section of memory for storage
of the check bits separate from that the section of memory storing
data information.
This subclass is indented under subclass 763. Subject matter in which there is more than one storage device,
each storing more than a single digit of data.
This subclass is indented under subclass 769. Subject matter where the storage medium is essentially of
a two dimensional shape with one dimension being very long in relation
to the other.
This subclass is indented under subclass 763. Subject matter where the storage device is or contains a
solid state device (e.g., an integrated circuit or transistor).
This subclass is indented under subclass 752. Subject matter in which the error-correction capability
of the system is adapted to the existing error rate by selection
of encoding format.
This subclass is indented under subclass 752. Subject matter in which a lack of synchronization between
encoder and decoder is detected and/or corrected.
This subclass is indented under subclass 752. Subject matter where plural encoded data streams are simultaneously
transmitted over a common transmission medium in such a manner that
the information signals may be discretely recovered, wherein each
data stream contains one or more bytes preceded by an address header
or where the simultaneously transmitted plurality of data streams
include synchronization or other control information.
This subclass is indented under subclass 752. Subject matter where there are m information code elements
and k error check code elements such that there are sufficient check
elements to correct a single error and the k check elements are
determined by even parity checks in conjunction with element values
appearing in certain selected information positions where each of
the elements of the code group must be in a parity check subgroup
with one or more of the check elements and no two different code
elements having exactly the same set of check elements associated
with it.
(1)
Note. See U.S. Patent RE23601, columns 5-9, for a more rigorous
definition.
This subclass is indented under subclass 752. Subject matter where, during error correction, in addition
to an error correcting code, use is made of information about the
reliability of the decoding of a particular bit.
This subclass is indented under subclass 752. Subject matter where a code word c(x), where x is a unit
delay operator, is generated by dividing a delayed version of the
data polynomial d(x), i.e.,. xnd(x), by a generator polynomial, g(x),
and subtracting the remainder from the delayed version of the data
polynomial, thereby producing a code word that is a multiple of
the generator polynomial, and where the data polynomial d(x) is
such that positions within the block correspond to powers of x and data
values at the positions correspond to polynomial coefficient values.
This subclass is indented under subclass 781. Subject matter where the block code is a t error correcting
code which is the set of all polynomials [a(c)] over
the Galois field GF( 2m) of degree n-1 or less, such that a(ai)=0,
for i=1,3,5,..., 2t-1 where a is a primitive element of
the finite field GF( 2m), and where c is the radix 2 for binary
data, a(c)=a0+a1c+a2c2+...+an-1cn
- 1, and aj=0,1 (j=0,1,2,..., n-1 ).
This subclass is indented under subclass 781. Subject matter where the block code is an (n, k, t) type
polynomial code in which each code word is n=23 bits long,
contains k=13 data or information bits, corrects up to
t=3 errors, and the code word also contains (n-k)=10
redundant check bits.
This subclass is indented under subclass 781. Subject matter where the block code consists of K data and
N-K check symbols, where N is an arbitrary number and K is less
than N, and where each symbol is made of J binary bits encoded with
a generator polynomial g(x) for the code and a field generating
polynomial M(x) which defines the Galois field.
This subclass is indented under subclass 781. Subject matter where decoded data is divided by an inverse
of the generator polynomial to obtain a data word of 1 bit which
indicate which bits of the decoded data are in error.
This subclass is indented under subclass 746. Subject matter in which information bits are encoded to
generate a plurality of check bits, each check bit is generated
as a function of a different plurality of information bits and is interspersed
among the information bits at predetermined intervals with no natural
beginning point or ending point (i.e., there is no length restriction
for the encoded data).
(1)
Note. Convolutional coding means adding to the information
a repeating sequence that is known to the receiver. By subtracting
this repeating sequence and performing other tests, the receiver can
determine what should have been received with a high degree of accuracy.
(2)
Note. This subclass includes forward error correction, per
se, (i.e., the receiver corrects the error without requiring any further
information from the sender, which requires a minimum amount of redundancy
in the transmission since not only must an error be detected, but
its location must be determined) and forward error correction with
the assistance of symbol reliability information.
(3)
Note. This subclass does not include demodulation decisions
based upon oversampling or on intersymbol interference alone.
(4)
Note. This subclass does not include channel equalization
or predistortion control based on correction results (e.g., decision
feedback equalization).
(5)
Note. This subclass does not include detection or correction
of errors produced by trial values, perturbations, predictions,
quantizations, estimations or approximations, which errors are used
as feedback for control of signal generation or coding (e.g., PID
controlling, source calibration, successive approximation A/D
conversion, DSV constrained encoding, predictive encoding).
(6)
Note. Forward error correction (FEC) is an error-correcting
technique that avoids the need for any reverse channel by enabling
self-correction of errors at the receiver by adding information
(at the expense of throughput) to enable the receiver to determine
what the error was and the correct information to substitute for
said error.
and 797, for various types of data correction such
as trial values, perturbations, predictions, quantizations, estimations
or approximations, which errors are used as feedback for control of
signal generation or coding.
This subclass is indented under subclass 786. Subject matter in which a lack of synchronization between
the encoder and decoder is detected and/or corrected.
This subclass is indented under subclass 786. Subject matter where single bits are periodically deleted
at intervals from a low-rate convolutional code.
This subclass is indented under subclass 786. Subject matter where a tree structure of the convolutional
code is used for searching locally a path which is considered to
be the most likely to produce a correct data sequence.
This subclass is indented under subclass 786. Subject matter where, for a convolutional code of k bits
length, an inverse coding operation is performed in which 2k-1 decision
bits are used to select an output bit and where after many branches,
the most probable path will be selected with a high degree of certainty,
and where the branches form a mesh pattern (i.e., branches start
at a plurality of points and intersect other branches).
Data Processing: Speech Signal Processing, Linguistics,
Language Translation, and Audio Compression/Decompression,
subclass 242 for Viterbi trellis speech recognition.
This subclass is indented under subclass 786. Subject matter where decoded data is divided by an inverse
of the generator polynomial to obtain a data word of 1 bit which
indicate which bits of the decoded data are in error.
This subclass is indented under subclass 786. Subject matter where a decoder selects the sequence out
of all the possible transmitted sequences which is most likely to
match the received data sequence and determines corresponding digital
(data) information.
Pulse or Digital Communications,
subclasses 262 and 341 for maximum likelihood decoding (other
than for error correction) in pulse or digital communication.
This subclass is indented under subclass 786. Subject matter where data is not decoded as soon as it is
received, instead, a sequence of data, having a predetermined decoding
depth, following the digit to be decoded is first collected, then,
by computing what are known as path metrics, a limited number of
possible messages are selected, each extending throughout the decoding
depth far beyond the digit presently to be decoded, with one such
survivor sequence ending in each of the data states.
Data Processing: Speech Signal Processing, Linguistics,
Language Translation, and Audio Compression/Decompression,
subclass 242 for Viterbi trellis speech recognition.
This subclass is indented under subclass 786. Subject matter where a tree of possible data sequences is
constructed identifying the possible data sequences in terms of
data states, and from which correlations are computed for selecting
the paths which are to survive to the next stage of decoding received
data.
This subclass is indented under subclass 746. Subject matter in which error correction is effectively
achieved by error masking (making error invisible at output) through
majority logic or voting techniques.
This subclass is indented under the class definition. Subject matter in which error detecting techniques are utilized
to detect an out-of-synch condition or to control synchronization between
devices.
This subclass is indented under the class definition. Subject matter in which a specific technique is recited
for detecting an error or fault condition.
This subclass is indented under subclass 799. Subject matter in which a redundant bit is added to a block
of data bits.
(1)
Note. This redundant bit or parity bit is of a logic state
to make the total number of bits having a predetermined logic state
within the block odd or even.
This subclass is indented under subclass 800. Subject matter wherein the parity scheme in the system includes
the generation of parity bits on both an even and odd basis.
This subclass is indented under subclass 800. Subject matter which calculates an expected parity value
prior to execution of an operation and is subsequently compared
to the actual parity value to detect an error.
This subclass is indented under subclass 800. Subject matter in which a single parity bit is derived from
data bits taken over each of two or more dimensions, such as horizontal
and vertical parity.
This subclass is indented under subclass 800. Subject matter in which the parity bit is calculated for
data bits read into or read out of an information signal storage
device. (1) Note. Address parity check arrangements are included
in this subclass.
This subclass is indented under subclass 799. Subject matter in which a code constraint of a constant-ratio
between bits of a first logic state and a second logic state is
utilized to enable error/fault detection.
This subclass is indented under subclass 799. Subject matter in which a check character, derived as a
predetermined function of a group of data bits, is associated with
the group of data bits for error detection purposes.
This subclass is indented under subclass 807. Subject matter in which a check character, calculated as
the remainder after the value of the digital data is divided by
a modulus-n, is associated with the digital data to enable error/fault detection.
This subclass is indented under subclass 799. Subject matter in which the digital data encoding scheme
provides inherent constrained conditions which are monitored to
enable error/fault detection.
This subclass is indented under subclass 809. Subject matter in which the digital data is encoded in a
multilevel or multistate format where the number of levels or states
is greater than 2.
This subclass is indented under subclass 799. Subject matter in which a forbidden combination of digital
data or improper condition of a device is monitored to enable error
or fault detection.
This subclass is indented under subclass 811. Subject matter in which the forbidden combination is either
a specified pattern of digital data or a count of one or more types
of digital pulses.
This subclass is indented under subclass 811. Subject matter in which the improper condition is the simultaneous
activation of two or more keys on a data input device.
This subclass is indented under subclass 811. Subject matter in which the timing or clocking of digital
data is monitored to detect a predetermined forbidden combination
or condition.
This subclass is indented under subclass 811. Subject matter in which the time delay between events or
data is detected to determine a predetermined forbidden condition.
This subclass is indented under subclass 811. Subject matter in which both the true and complement state
of each logic function is provided and the simultaneous occurrence
of both states indicates a forbidden combination.
This subclass is indented under subclass 811. Subject matter in which the forbidden condition is the presence
of noise exceeding a predetermined level.
This subclass is indented under subclass 811. Subject matter in which the improper combination is a missing
bit or dropout of a bit within a data character.
Television Signal processing for Dynamic Recording
or Reproducing,
subclasses 2+ and 47+ for drop-out detecting or correcting
in the processing of a television signal.
This subclass is indented under subclass 819. Subject matter in which the data from plural parallel devices
or channels is compared to detect an error or fault.
This subclass is indented under subclass 820. Subject matter which detects an error or fault in a device
including a channel of a transmission medium with a device for supplying
a digital signal thereto.
This subclass is indented under subclass 822. Subject matter in which the data being transferred and compared
comprises both the true and complement bit states of the data.
This subclass is indented under subclass 819. Subject matter in which the error/fault detection
is enabled by comparing the device output with the device input.
for diagnostic apparatus testing which includes
comparison of the device output with the device input.
E-SUBCLASSES
The E-subclasses in U. S. Class 714 provide f or processes
and apparatus for detecting errors in data-processing including
processes and apparatus for monitoring and evaluating data-processing
equipment; processes and apparatus for correcting data-processing errors
or for responding to faults in data-processing equipment; and processes
and apparatus for avoiding data-processing errors and faults in
data-processing equipment.
This main group provides for processes and apparatus for
the detection or correction of data-processing errors including
the monitoring and evaluation of data-processing equipment. This
subclass is substantially the same in scope as ECLA classification G06F11/00.
Foreign art collections including subject matter
in which digital logic is designed for improved test ability by
including shift register latches (SRL) to enable the configuring of
the circuitry in combinational logic form.
Foreign art collections including subject matter
in which the specific means or method of generating a test pattern
for an error checking system is claimed.
Foreign art collections including subject matter
in which a plurality of information bits are encoded to generate
a plurality of check bits as a function of the information bits
with the information bits and check bits being associated together
to form a block code.
Foreign art collections including subject matter
in which digital data being written into or read out of a storage
device is encoded in a block code format.
Foreign art collections including subject matter
in which the information bits are encoded to generate a plurality
of check bits, each check bit is generated as a function of a different
plurality of information bits and is interspersed among the information
bits at predetermined intervals with no natural beginning point
or ending point as in block codes.
Foreign art collection for subject matter in which
a signal or circuit parameter is monitored to provide an indication
of an imminent error or fault condition prior to its actual occurrence.
Foreign art collection for subject matter in which
the spare apparatus includes a channel of a transmission medium
with a device for supplying digital data thereto.
Foreign art collection for subject matter in which
the faulty apparatus includes a device for performing a calculation
or arithmetic operation on the data signal.
Foreign art collection for subject matter in which
the diagnostic testing is performed upon a program controlled device
for performing a calculation or arithmetic operation on the data
signal.
Foreign art collection for subject matter which
tests a system by substituting a microprocessor, to simulate the
operation of the system microprocessor to control diagnostic testing
of the system.
Foreign art collection for subject matter which
tests the processor by requiring periodic updating of a time monitoring
device within a preset time interval known as a window.
Foreign art collection for subject matter in which
the processor or computer being tested is located within a diverse
device (e.g., a microwave oven or photocopier) machine.
Foreign art collection for subject matter in which
the errors or faults detected are registered or recorded to present
a history for diagnostic purposes.
Foreign art collection for subject matter in which
the testing is performed under control of a maintenance module or
subsystem which independently monitors and performs fault diagnosis
of a programmable digital computer.
Foreign art collection for subject matter in which
error detecting techniques are utilized to detect an out-of-sync
condition or to control synchronization between devices.
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