PROJECT TITLE : Verified VHDL Synthesizable Cores
TECHNICAL ABSTRACT (LIMIT 200 WORDS)
The development of verified reusable hardware specification components, manifest as synthesizable VHDL cores, represents a key technology that will enable engineering discipline to manage design complexity. The specific innovation we propose is the development of verified, synthesizable VHDL cores that include all the features, documentation, and support necessary to insure integration with customer designs with the high degree of reliability provided by the application of formal methods. The innovation is relevant to NASA as (i) an innovative approach to software and systems reuse, (ii) formal mathematical methods for specification, design, and analysis of digital systems, and (iii) techniques and tools for integrating formal methods with existing methods, tools, and languages. The technology will provide a means by which there are no tradeoffs between COTS (commercial off the shelf) components and those required to satisfy the stringent reliability and safety requirements of safety-critical systems.POTENTIAL COMMERCIAL APPLICATIONS
The POTENTIAL COMMERCIAL APPLICATION is in the electronics design industry for both safety-critical and commercial systems. These products will be used by engineers within the computer, networking and semiconductor markets to develop reusable designs, reduce design cycle times and reduce time to market for electronic products and systems.NAME AND ADDRESS OF PRINCIPAL INVESTIGATOR
Dr. Bhaskar BoseNAME AND ADDRESS OF OFFEROR
Derivation Systems, Inc.
5963 La Place Court, Suite 208
Carlsbad, CA 92008
Derivation Systems, Inc.
5963 La Place Court, Suite 208
Carlsbad, CA 92008