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Aliases:

None

Technical Challenge:

Provide sufficient decoupling capacitance physically close to the processor.

Description:

This method can be used to build decoupling capacitors with high capacitance values, low parasitic losses, good yield, and long-term reliability. The fabrication method can also manufacture other passives such as inductors and resistors; as well as interconnect lines. The invention enables high yielding capacitors and other passive elements to be placed very close to the processor or other integrated circuit design and provides improved signal integrity for high frequency processing. Additionally, it allows multiple passive components to be integrated into a single module, reducing cost and increasing yields for RF systems.

Demonstration Capability:

None available at this time

Potential Commercial Application(s):

Supercomputing applications, high-speed processor systems, hand held electronics (cell phones, pagers, etc.)

Patent Status:

Patent Application has been filed with USPTO. (Updated)

Reference Number: 1352

If you are interested in exploring this technology further, please call 443-445-7159 or express your interest in writing to the:

National Security Agency
NSA Technology Transfer Program
9800 Savage Road, Suite 6541
Fort George G. Meade, Maryland 20755-6541