Project Title:
Focal-Plane Processing of Visual Information
07.04-1112
Focal-Plane Processing of Visual Information
Q-DOT Inc.
1069 Elkton Drive
Colorado Springs
CO
80907
Roberts
Peter C. T.
NAS1-18287
Amount:
LaRC
NAS1-17940
Abstract:
A Phase II follow-on program is proposed based on the good results generatedin the Phase I program. An actual layout was performed in the Phase I program showing
that a 128 x 128 x 3 mil square focal-plane processor (FPP) chip is feasible. The
performance of that FPP and an improved hexagonal symmetry version will be studied
with actual test chip measured data from the Phase II tasks. Support hardware is
to be assembled using low-cost standard components and a full system definition developed
for the Phase III subsequent program. Optical performance will be determined by
a combination of test chip measurements and analytic and computer simulation method.
Reasonable expectations of device yield indicate that working versions of 32 x 32,
64 x 64, and 128 x 128 array FPP will be achieved. Throughput of the final optimized
FPP using the brick-wall architecture is expected to greatly outperform conventional
approaches to visual information acquisition and initial processing for computer
and/or robotic vision systems. Frame rate of 100 to 1,000 per second at grey-scale
(four to six bits) resolution are possible at > 1 GOPS throughput.