Project Title:
Optimal Systolic Architectures for the Navier-Stokes Equations
06.01-3030K
Optimal Systolic Architectures for the Navier-Stokes Equations
Zeroone Systems Inc.
2431 Mission College Blvd
Santa Clara
CA
95054
Fok
Simon K.
NAS2-12444
Amount:
ARC
NAS2-12082
Abstract:
The objective is to construct a Systolic Navier-Stokes Attached Processor(SNAP) connected to a VAX computer for high speed NASA flow code computations. A
high level architecture for the SNAP has been designed. The architecture consists
of: (1) a narrow bandwidth linear solver which is currently under development for
NASA by ZeroOne Systems, Inc. and (2) fast Fourier transform modules and matrix-vector
multiplier modules which will be constructed using Sky Computers' Sky Warrior array
processors. All these processors will be integrated with the host computer through
the Apter DPS-2400 which is, in essence, a shared memory multiprocessor. The three
NASA flow codes already studied will be mapped into the SNAP. This involves restructuring
of the whole computational process in each code to facilitate systolic chaining;
the actual computational algorithm will not be changed. Software will also be developed
to coordinate the operations of multiple processors, shared memory and the host using
low-level interprocessor communication primitives to create
semaphores, critical regions and other synchronization primitives to ensure reliable
operations of the SNAP. Cost-effectiveness of the SNAP with respect to a range of
computers will be assessed.