Supercomputing Architecture
At the broadest level, the architecture
effort seeks to assure Sandia and the ASC program of continuity in the supply
of supercomputers. Given the small size of the US supercomputer industry
at the very high end, this often includes leading industry through advances
in supercomputing technology. Dating to 15 years ago, Sandia has acquired
leading Massively Parallel Processor (MPP) supercomputers
of a consistent architecture from nCUBE, Intel, and Cray. Over this period, Sandia
has increasingly performed the research and development to keep this architecture
current and now has the ability to implement this architecture with minimal
dependence on vendors. The architecture effort is currently exploring architectural
issues necessary to scale to the 1-100 PFLOPS level.
Areas of Research:
- Advanced Architectures
- Studies of radiation transport
algorithms on advanced computer architectures, such as Processor-In-Memory
(PIM), and comparison with existing architectures.
(Contact: Erik
P. DeBenedictis)
- Collaboration with Caltech
on architecture of PIM systems, including FPGA-based simulator.
(Contacts: Keith
D. Underwood, Thomas Sterling -
Caltech)
- Architecture of PIM systems,
including applications performance. Collaboration with University of
Notre Dame.
(Contacts: Peter Kogge -
Univ. of Notre Dame, Arun Rodriguez -
Univ. of Notre Dame, Richard Murphy -
Univ. of Notre Dame and Erik
P. DeBenedictis)
- Microarchitecture modeling
of supercomputer codes and implications to microarchitecture design.
Collaboration with New Mexico State University.
(Contacts: Jeanine
Cook - NMSU and Erik
P. DeBenedictis)
- Studies of fast floating point
algorithms using FPGA technology.
(Contact: Keith
D. Underwood)
- Modeling Advanced Architectures
with FPGA technology.
(Contacts: Keith
D. Underwoodand K.
Scott Hemmert)
- Algorithm Scalability
- Network Technology
- Systems Reliability
- Hardware failure rate of ASC-sized
supercomputers.
(Contact: Erik P. DeBenedictis)
- Changes in the impact of Cosmic-Ray
induced soft errors on ASC-sized supercomputers with semiconductor evolution
according to Moore’s Law.
(Contact: Erik P. DeBenedictis)
Program Contact: Neil D. Pundit
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