Project Title:
A High-Sensitivity, Charge-Coupled-Device Readout Technique
08.11-1112
911430
A High-Sensitivity, Charge-Coupled-Device Readout Technique
Q-Dot, Inc.
1069 Elkton Drive
Colorado Springs
CO
80907-3579
David W.
Gardiner
719-590-1112
GSFC
NAS5-31924
152
08.11-1112
911430
Abstract:
A High-Sensitivity, Charge-Coupled-Device Readout Technique
The low-noise performance of charge-coupled-device (CCD) imagers and signal-processing
devices is presently limited by the performance of the associated charge-sensing
amplifiers. Typical amplifiers show noise levels of 100 to 200 electrons/packet and
gains of 1 to 5 V/electron. The transverse floating-gate FET investigated in this
project will circumvent the gain-limiting stray capacitance and permit the development
of amplifiers with 100 to 200 V/electron gain with noise levels of less than five
electrons. The design of the device involves the integration of a PNP FET directly
above the active buried-channel region of the CCD. The PNP drain current travels
across the surface of the CCD channel and is modulated by passing the buried-channel
CCD charge packets under the FET. The doping profile of the device is designed to
isolate the holes in the transverse FET current from the electrons in buried-channel
CCD charge packets. The operating frequency of the device is limited by the width
of the CCD channel, but is expected to provide operation at 1 - 10 megasamples (Ms/s)
per second with 10,000 electron charge capacity.
The high gain and low noise of the proposed transverse floating-gate transistor is
applicable to virtually all high-performance CCD devices. In addition to improving
the sensitivity of CCD amplifiers, the device is an excellent building block for
the development of charge-mode analog-to-digital converters with 10 to 20 electron
least-significant-bit performance.
CCD, amplifier, FET, charge sensing