NASA STTR 2004 Solicitation

FORM B - PROPOSAL SUMMARY


PROPOSAL NUMBER: 04 T1.01-9991
RESEARCH SUBTOPIC TITLE: Information Technologies for System Health Management, Autonomy and Scientific Exploration
PROPOSAL TITLE: A System Level Tool for Translating Software to Reconfigurable Hardware
SMALL BUSINESS CONCERN (SBC) RESEARCH INSTITUTION (RI)
NAME:BINACHIP, INC. NAME:University of Illinois at Chicago
ADDRESS:2130 Chandler Lane ADDRESS:851 South Morgan St.
CITY:Glenview CITY:Chicago
STATE/ZIP:IL60026-5744 STATE/ZIP:IL60607-7043
PHONE:(847)657-8749 PHONE:(312)996-8249

PRINCIPAL INVESTIGATOR/PROJECT MANAGER (Name, E-mail, Mail Address, City/State/Zip, Phone)
Prith Banerjee
prith@uic.edu


(847)757-8708

TECHNICAL ABSTRACT (LIMIT 200 WORDS)
In this research we will develop a system level tool to translate binary code of a general-purpose processor into Register Transfer Level VHDL code to be mapped onto FPGA-based reconfigurable hardware. We further plan to study techniques for performing hardware/software co-design on integrated systems-on-a-chip platforms consisting of embedded processors, memories and FPGAs. Finally we will develop techniques to perform area, delay and power tradeoffs in the hardware that is synthesized by our compiler on the FPGAs. We will demonstrate our concepts using a prototype compiler that will translate binary code of a Texas Instrument TMS320 C6000 processor into a hardware/software implementation on a Xilinx Virtex II Pro Platform FPGA. This work will be performed jointly between BINACHIP, a small business company, and University of Illinois at Chicago, a partner research institution

POTENTIAL NASA COMMERCIAL APPLICATIONS (LIMIT 100 WORDS)
NASA is pursuing its missions through high visibility projects such as: (1) the Space Shuttle and the International Space Station that will help humans explore the Moon, the Mars, and beyond (2) the Earth Observing System such as the EOS Aura that will study the ozone layer and its impact on the environment (3) the Spirit and Opportunity Rovers that will explore Mars and prepare for a manned mission to Mars (4) Deep Space Missions such as the Hubble, Chandra and Spitzer Orbiting Observatories that will help us understand the Milky Way and other galaxies. All these projects have one thing in common; they require a lot of sophisticated image processing operations on images captured by various cameras that require high performance implementations. Interest in targeting FPGAs for high performance hardware-based implementations is growing. The major roadblock to obtaining this performance is the lack of sophisticated tools. The BINACHIP compiler will be useful in developing these FPGA based hardware applications by taking software implementations of sophisticated image processing applications and migrating them to hardware implementations. Possible customers for the BINACHIP compiler within NASA include the Ames Research Center, Langley Research Center, the Jet Propulsion Laboratory, Goddard Space Flight Center, Dresden Flight Center, and others.

POTENTIAL NON-NASA COMMERCIAL APPLICATIONS (LIMIT 100 WORDS)
The software that will be developed by BINACHIP will have two general application areas (1) embedded systems software (2) electronic design automation. Increasing demands for cell-phones, PDAs, and network devices have provided opportunities for the growth of embedded software, operating systems and development tools vendors. The embedded systems software market is expected to become $21 billion in 2005. As newer processor architectures are announced, there is a need to reuse and migrate the software from older generation processors to newer processors. The BINACHIP compiler will be useful to these companies to assist in the task of software migration. The second commercial area for BINACHIP is electronic design automation (EDA) that is expected to become a $6 billion market in 2005. One of these segments is that of system level EDA, which is expected to grow to at least $300 million by 2005. The BINACHIP compiler will enable translation of software from a general-purpose processor onto a system-on-chip consisting of processors, memories and FPGAs.