|
Award Abstract #0619223
MRI: Acquisition of an Ultra Low-Latency Multiprocessor System with On-Board Hardware Accelerators
| NSF Org: |
CNS
Division of Computer and Network Systems
|
|
|
| Initial Amendment Date: |
August 10, 2006 |
|
| Latest Amendment Date: |
August 10, 2006 |
|
| Award Number: |
0619223 |
|
| Award Instrument: |
Standard Grant |
|
| Program Manager: |
Rita V. Rodriguez
CNS Division of Computer and Network Systems
CSE Directorate for Computer & Information Science & Engineering
|
|
| Start Date: |
August 15, 2006 |
|
| Expires: |
July 31, 2009 (Estimated) |
|
| Awarded Amount to Date: |
$330000 |
|
| Investigator(s): |
Laxmi Bhuyan bhuyan@cs.ucr.edu (Principal Investigator)
Walid Najjar (Co-Principal Investigator)
Gianfranco Ciardo (Co-Principal Investigator)
|
|
| Sponsor: |
University of California-Riverside
Office of Research
RIVERSIDE, CA 92521 951/827-5535
|
|
| NSF Program(s): |
UNDISTRIBUTED PANEL/IPA FUNDS,
COMPUTER SYSTEMS ARCHITECTURE,
MAJOR RESEARCH INSTRUMENTATION
|
|
| Field Application(s): |
0000912 Computer Science
|
|
| Program Reference Code(s): |
HPCC, 9218, 4715, 1189
|
|
| Program Element Code(s): |
9199, 4715, 1189
|
ABSTRACT
This project, acquiring an extremely low-latency multiprocessor system with on-board hardware accelerators, develops efficient scalable algorithms and software resource management schemes for individual applications. The cluster will be used in support of the following projects.
-Investigation into scalable hardware and software design for Internet web servers and data centers,
-Symbolic model checking,
-Pattern discovery for biological applications,
-Automatic compilation of high-level code, such as C or Fortran, into RTL VHDL code,
-Warp processing, and
-Augmenting existing microarchitecture with security protections ensuring integrity & confidentiality of program execution.
The proposed cluster can be partitioned into several subclusters that can work independently and simultaneously on different applications, provides ultra low message passing latency within a sub-cluster and between sub-clusters, and provides an SMP environment with processors that can be used for tightly-coupled codes; thus a hybrid programming model suits different applications. The research projects on FPGA compilation, hardware/software partitioning, and CPU micro architecture design require an FPGA-based system for a test bed.
Please report errors in award information by writing to: awardsearch@nsf.gov.
|
