This class provides, within an electrical computer or digital data processing system, for the
following subject matter:
A. Processes and apparatus for addressing memory wherein
the processes and apparatus involve significant address manipulating
(e.g., combining, translating, or mapping and other techniques for
formatting and modifying address data)
and are combined with specific memory configurations
or memory systems;
B. Processes and apparatus for accessing and controlling memory (e.g., transferring and modifying address data, selecting storage devices,
scheduling access); and
C. Processes and apparatus for forming memory addresses
(e.g., virtual memory addressing, address translating, translation-lookaside
buffers (TLBs), boundary checking, and page mode).
SCOPE OF THE CLASS
(1)
Note. In the instance where a peripheral is a memory, classification herein is proper.
(2)
Note. Classification herein requires more than nominal recitation
of addressing techniques or of memory accessing
or controlling in combination with digital data processing
systems or data processing.
A nominal combination refers to a combination wherein one or more
of the means or steps thereof are recited so broadly, and without
details, as to constitute a mere identification rather than a description
of each means or step.
(3)
Note. Memory devices, per
se, are classified in their respective device classes. More specifically,
registers and data bearing records
(e.g., smart cards) are classified elsewhere. Static memory devices including internal elements
of memories are classified elsewhere.
Display memory organizations and
structures (i.e., selective visual display systems) such as memories defined by graphics processing
systems and graphics processing that involves interfacing with memory are classified elsewhere. Devices
(e.g., printers) that include memory for processingdata for
static presentation (i.e., for viewing on a fixed medium such as
paper) are classified elsewhere. Dynamic magnetic information storage
or retrieval devices (e.g., magnetic disks, tapes, drums, etc.)
are classified elsewhere. Dynamic information storage or retrieval devices
(e.g., optical disks, CD-ROMs, jukebox mechanics, and other storage devices
having magnetic and mechanical components) are classified elsewhere.
See the SEARCH CLASS notes below.
(4)
Note. Processes and apparatus for transferring data between memories of
different computers directly (i.e.,
with minimum or no intervention from main processors of
the computers) are classified elsewhere.
See the SEARCH CLASS notes below.
(5)
Note. Processes and apparatus for direct memory access (DMA)
(i.e., the transferring of data between peripherals and memories of
a computer or digital data processing system with minimal or
no intervention from the main processor of
the computer or digital data processing system) are classified
elsewhere. See the SEARCH CLASS notes below.
(6)
Note. Processes and apparatus for accessing and retrieving instruction data of a fixed or variable
length from a memory or buffer and
for shifting such instruction data to align
it with a physical memory or buffer boundary
are classified elsewhere. See the SEARCH CLASS notes below.
Registers, various subclasses for basic machines and associated
indicating mechanisms for ascertaining the number of movements of
various devices and machines; machines made from these basic machines alone
(e.g., cash registers, voting machines) and in combination with
various perfecting features such as printers and recording means;
and various systems controlled by data bearing records
(e.g., smart cards).
Active Solid-State Devices (e.g., Transistors, Solid-State
Diodes),
subclass 202 for repeating geometric arrangement of individual
structural elements of solid-state devices, and subclasses 368 and
390 for matrix or array of field effect transistors (FETs).
Electronic Digital Logic Circuitry,
subclasses 37+ for multifunctional or programmable logic (e.g.,
gate arrays) and subclasses 52+ and 104+ for generic
logic functions such as EXOR, AND, OR, NOT and decoding in general.
Communications: Electrical,
subclasses 825 through 825.98for controlling one or more devices to obtain a
plurality of results by transmission of a designated one of plural
distinctive control signals over a smaller number of communication
lines or channels, particularly subclasses 2.1-2.8 for path selection,
subclasses 3.1-3.9 for communication systems where status of a controlled
device is communicated, subclasses 14.1-14.69 for selective decoder
matrix, subclass 825.02 for tree or cascade selective communication,
subclasses 825.2-825.21 for synchronizing selective communication
systems, subclasses 825.52 and 825.53 for selective communication
addressing, and subclasses 825.57-825.69 for pulse responsive actuation.
Coded Data Generation or Conversion, various subclasses for electrical pulse and digit code
converters (e.g., systems for originating or emitting a coded set
of discrete signals or translating one code into another code wherein the
meaning of the data remains the
same but formats may differ).
Computer Graphics Processing and Selective Visual
Display Systems,
subclasses 1.1 through 3.4for visual display systems with selective electrical
control including display memory organization and structure for
storing image data and manipulating image data between a display
memory and display peripheral, subclasses 530-574 for memory
organization and structure for storing images to be displayed,
and subclass 521 for graphic processing that involves interfacing
with memory.
Facsimile and Static Presentation Processing,
subclasses 1.16 and 1.17 for process and apparatus (e.g., printer)
that includes memory for processing data for static presentation
(i.e., for viewing on a fixed medium such as paper).
Dynamic Magnetic Information Storage or Retrieval, (which is an integral part of Class 369 following
subclass 18 ), for record carriers and systems wherein data are stored and retrieved by interaction
with a medium and there is relative motion between a medium and a
transducer (e.g., magnetic disk drives, tapes, and drums and control
thereof, per se), particularly subclasses 72.1+ for locating
a specific area in storage.
Electricity: Electrical Systems and Devices,
subclasses 684+ for computer storage
component combined with housing or mounting arrangement having no data processing or calculating procedures.
Static Information Storage and Retrieval, various subclasses for static memory devices including
internal elements of the memory,
particularly
subclass 189.011 for read/write circuits and subclasses
230.01+ for addressing of addressable, static single
storage elements or plural elements; subclass 189.05 for buffering or
latching data being read from
or written to memory; subclass 189.08
for logic devices in combination with memory systems;
subclasses 200 and 201 for testing of memory systems; and
subclass 230.08 for buffering and latching address
data being employed to access memory.
Dynamic Information Storage or Retrieval, various subclasses for record carriers and systems wherein
data are stored and retrieved by interaction with a medium and there
is relative motion between a medium and a transducer (e.g., optical
disks, CD-ROMs, jukeboxes), particularly
subclasses 30.01 through 41.01,69, and 176-271 for designating or selecting storage
media to be used for storage and retrieval.
Multiplex Communications, appropriate subclasses for multiplex switching techniques
similar to addressing and the handling of memory information signals
and for the simultaneous transmission of two or more signals over
a common medium, particularly 351 for time division multiplex (TDM)
switching,
subclass 395.7 for an ATM network with detail of storage access
and control, subclasses 475+ for asynchronous TDM communications
including addressing, and subclasses 498+ for time division
bus transmission.
Data Processing: Vehicles, Navigation, and Relative
Location, appropriate subclasses for applications of computers in vehicular and navigational
environments.
Data Processing: Generic Control Systems or Specific
Applications, appropriate subclasses and particularly
subclasses 1 through 89for data processing generic control systems and subclasses
90-306 for computer and data processing system applications.
Data Processing: Measuring, Calibrating, or Testing,
subclass 80 for specified memory location generation for storage
of an electrical signal parameter measurement.
Data Processing: Speech Signal Processing, Linguistics,
Language Translation, and Audio Compression/Decompression,
subclasses 1+ for applications of computers in
linguistics, subclasses 200+ for applications of computers in speech signal processing,
and subclasses 500 through 504 for applications of computers in audio
compression/decompression.
Data Processing: Financial, Business Practice, Management,
or Cost/Price Determination, appropriate subclasses for applications of computers and calculators in business
and management environments.
Data Processing: Database and File Management
or Data Structures,
subclasses 1+ , 100+, and 200+ for data retrieval, file or database management,
garbage collection, file configuration and initialization, and allocation.
Electrical Computers: Arithmetic Processing and
Calculating,
subclasses 1+ for electric hybrid computers; subclasses 100+ for
electric digital calculating computers; and subclasses 800+ for
electric analog computers.
Electrical Computers and Digital Processing Systems:
Multicomputer Data Transferring or Plural or Processor Synchronization, appropriate subclassesfor multiple computer data transfer, particularly
subclass 212 for computer-to-computer direct memory accessing and
subclasses 213-216 for multicomputer data transfer via shared memory.
Electrical Computers And Digital Data Processing
Systems: Input/Output,
subclasses 1+ for transferring data from one or more peripherals
to one or more computers for the latter to process, store, or further
transfer or for transferring data from the computers to the peripherals,
particularly subclasses 22+ for direct memory access (DMA)
(i.e., the transferring of data between peripherals and memories
of a computer or digital data processing system with minimal or
no intervention from the main processor of the computer or digital
data processing system).
Electrical Computers And Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g., Processors),
subclasses 1+ for processing architectures such as MIMD, vector,
or array processors; subclass 204 for instruction alignment; subclasses
205+ for instruction fetching;and subclasses 200 through
248 for various instruction processing not involving I/O
such as executing.
Electrical Computers and Digital Processing Systems:
Support,
subclass 150 and 181 for multiple computer communication using
cryptography; and subclasses 187 and 188 for software program protection
or computer virus detection in combination with data encryption.
Error Detection/Correction and Fault
Detection/Recovery, various subclasses for detecting or correcting errors in
generic electrical pulse or pulse coded data and for detecting and recovering
from faults of computers, digital data processing systems, and logic
level based systems, particularly
subclass 702 for memory access (e.g., address permutation);
subclasses 710+ for replacement with spare memory components
or portion thereof; subclasses 718+ for memory testing;
and subclasses 763+ for memory access with error correction,
error pointer, or error checking.
Robots, appropriate cross-reference art collections for
reprogrammable, multifunction manipulators designed to move devices.
SECTION III - GLOSSARY
The terms below have been defined for purposes of
classification in this class and are shown in underlined
type when used in the class and subclass definitions.
When these terms are not underlined in the definitions, the meaning
is not restricted to the glossary definitions below.
ADDRESS DATA
Data that specify a location
in a memory.
BUS
A conductor used for transferring data,
signals, or power.
COMPUTER
A machine that inputs data,
processes data, stores data, and outputs data.
DATA
Representation of information in
a coded manner suitable for communication, interpretation, or processing. See ADDRESS DATA, INSTRUCTION
DATA, STATUS DATA, and USER DATA in this glossary,
DATA PROCESSING
See PROCESSING below.
DIGITAL DATA PROCESSING SYSTEM
An arrangement of processor(s) in
combination with either memory or peripherals, or both, performing data processing.
INFORMATION
Meaning that a human being assigns to data by
means of the conventions applied to that data.
INSTRUCTION DATA
Data that represent an
operation and identify its operands, if any.
MEMORY
A functional unit to which data can
be stored and from which data can
be retrieved.
PERIPHERAL
A functional unit that transmits data to
or receives data from a computer to which it is coupled (e.g.,
modems, keyboards, monitors, touch tablet, printers, joy stick, disk
and tape drives, etc.).
PROCESSING
Methods or apparatus performing systematic operations upon data or information exemplified
by functions such as data or information transferring, merging, sorting, and
calculating (i.e., arithmetic operations or logical operations).
Note: In an effort to avoid redundant constructions, in this
class, where appropriate, the term address
dataprocessing is used
in place of address datadata processing.
PROCESSOR
A functional unit that interprets and executes instruction data.
STATUS DATA
Data that represent conditions
of data, computers, peripherals, memory,
etc.
USER DATA
Data other than address data, instruction
data, or status data.
ADDRESSING COMBINED WITH SPECIFIC MEMORY CONFIGURATION
OR SYSTEM:
This subclass is indented under the class definition. Subject matter comprising means or steps for determining
one or more values (i.e., address data)
that specify one or more locations in a storage medium wherein the
means or steps are claimed in combination with a particular configuration
or system for storing data.
(1)
Note. Classification herein requires significant address manipulating
(i.e., more than nominal recitation of an addressing technique).
Significant address manipulating is exemplified by address
dataprocessing functions
such as combining, translating, mapping, and other techniques associated
with forming or modifying address data.
(2)
Note. Means or steps for determining a value that specifies
a memory location (i.e., address data) must include more than nominal
recitation of processing functions
and memory components for classification
herein.
(3)
Note. This subclass and those indented below provide for
combinations of data processing,
particular memory systems, and significant address data manipulating. Generalized
addressing in a digital data processing system is
classified elsewhere in this class. See the SEARCH THIS CLASS,
SUBCLASS notes below.
(4)
Note. This subclass and those indented below may include
means (e.g., processor, controller,
etc.) or steps for control of a memory of
a digital data processing system in
combination with memory accessing
(e.g., reading, writing). Memory accessing
and control for specific memory compositions,
hierarchical memory configurations,
and shared memory, however, is classified
elsewhere. See the SEARCH THIS CLASS, SUBCLASS notes below.
(5)
Note. Means or steps for accessing and controlling plural memory configurations (e.g., data farms, "library" systems) that
include significant data processing are
classified herein. Control systems for delivering storage media
(e.g., delivery of robotics or automated tapes or cartridges, selection
and delivery of platters), however, are properly classified elsewhere
under automated control or another appropriate subclass in the respective
device, robotics, and generic control classes. In instances involving significant data processing and significant details
of media delivery systems, classification herein is proper.
through 116, for storage accessing and control for
various memory compositions (e.g.,
ROM, RAM, CAM, dynamic, detachable, bubble, etc.) with more than
nominal data processing.
Computer Graphics Processing and Selective Visual
Display Systems,
subclasses 530 through 574for processing indices to locations (or addresses)
of stored data elements in a computer graphic processing system.
Static Information Storage and Retrieval,
subclasses 189.011 for read/write circuits, and subclasses 230.01+ for
addressing of addressable, static single storage elements
or plural elements of the same type.
Dynamic Information Storage or Retrieval,
subclasses 30.01 through 41.01,69, and 176-271, as appropriate, for subject matter
related to designation or selection of storage medium to be used
for storage and retrieval.
Multiplex Communications, appropriate subclasses for multiplex switching techniques
similar to addressing or the handling of memoryinformation signals.
Data Processing: Speech Signal Processing, Linguistics,
Language Translation and Audio Compression/Decompression,
subclasses 2+ for memory control
scheme combined with linguistics.
Data Processing: Database and File Management
or Data Structures, or Document Processing,
subclasses 1+ for database management and file management systems
including significant addressing, retrieval, or manipulation of
information contained within a database of a digital data
processing system or computer including searching, query
processing, information locating and retrieval techniques from a
file or database; subclasses 100+ for database schema types;
and subclasses 200+ for file maintenance operations, allocating
or deallocating memory space to files, garbage collection, and hierarchical
or tree filling systems.
Electrical Computers and Digital Data Processing
Systems: Input/Output,
subclasses 3 through 4for Input/Out addressing, subclass 9
for address assignment for configuring peripherals, subclasses 22-28
for direct memory accessing (DMA) and subclass 316 for system
intra-connecting switching.
This subclass is indented under subclass 1. Subject matter wherein addresses are determined for memory not normally accessible by a base
operating system, computer, or digital data processing system components.
(1)
Note. Classification here may include virtual addressing
techniques; however, virtual memory addressing
art which deals with logical addressing techniques as opposed to
addressing for physical enhancements, such as extended and expanded memory, is classified elsewhere in this
class.
This subclass is indented under subclass 1. Subject matter wherein addresses are generated for memory nearest a processor in
a hierarchical memory arrangement
(i.e., a cache memory arrangement).
(1)
Note. This subclass accommodates particular addressing techniques
for cache memory systems. Cache memory accessing and control (i.e., reading
and writing) are classified elsewhere in this class. See the SEARCH
THIS CLASS, SUBCLASS notes below.
This subclass is indented under subclass 1. Subject matter wherein address schemes are particular to
a data storage device requiring
relative motion between a data holding
medium and a recording mechanism such as disk, tape, or drum memory.
Dynamic Magnetic Information Storage or Retrieval, which is an integral part of Class 369, following
subclass 18 , for record carriers and systems wherein information is stored and retrieved by
interaction with a medium and there is relative motion between a
medium and a transducer (e.g., magnetic disk drive devices and control
thereof, per se). See Class 360, subclass 72.2 for addressing and control
of recording mechanism to locate the selected area.
Dynamic Information Storage or Retrieval, various subclasses for record carriers and systems wherein information
is stored and retrieved by interaction with a medium and there is relative
motion between a medium and a transducer. Particularly, see
subclasses 30.01 through 41.01for selective addressing of dynamic storage medium.
This subclass is indented under subclass 1. Subject matter wherein logical addresses are determined
and mapped (e.g., interleaving) across different physical memory arranged in blocks, banks, partitions,
etc.
(1)
Note. This subclass includes subject matter directed to static
column or static row handling in multiple physical memory module
addressing.
Static Information Storage and Retrieval,
subclasses 230.03 and 230.04 for subject matter including plural
banks or blocks and alternating between them.
This subclass is indented under subclass 1. Subject matter wherein addresses are determined in a memory
system accommodating addressing requirements for software emulation
of a target computer or digital data processing system on a base
computer or digital data processing system.
(1)
Note. Classification here includes virtual addressing techniques
(that is, for example, processing logical to physical (real, absolute)
address translation entries. Virtual memory addressing deals with
logical addressing techniques. Classificaiton here is proper if
there is significant virtual memory processing for systems accomodating
emulation of a tarte computer of digital data processin system on a
base computer or digital data processing system. Logical addressing
for physical enhancements, such as extended and expanded memory,
is classified elsewhere in theis class.
Electrical Computers and Digital Processing Systems:
Virtual Machine Task or Process Management or Task Management/Control,
subclass 1 for virtual machine task or process management.
This subclass is indented under the class definition. Subject matter comprising means (e.g., a processor,
a controller, etc.) or steps for governing memory in
a computer or digital
data processing system or the passage (e.g., reading, writing)
of data thereto.
(1)
Note. The subject matter of this subclass and the subclasses
thereunder provides for details of how memory is
accessed and controlled. Classification herein requires more than
nominal recitation of accessing or controlling memory in
the context of digital data processing systems or data processing. Examples of significant memory accessing and control data processing include transferring and
modifying memoryaddress
data, selecting memory devices
or memory locations, and scheduling memory accesses.
(2)
Note. Storage devices such as static memory devices,
holographic stores, disk drives (and the mechanical control of disk
drives, e.g., head positioning, substrate speed, etc.), and optical
stores, are classified, per se, in their respective device classes.
(3)
Note. Subject matter classified herein may include nominal
recitations of address data generation,
manipulation, and modification. Combinations of a particular memory construct (e.g., cache) with accessing
and control and significant addressing as exemplified by data processing functions such as combining, translating,
mapping, and other techniques associated with forming and modifying
addresses, however, are classified in superior subclasses directed
to such combinations. See the SEARCH THIS CLASS, SUBCLASS notes
below.
(4)
Note. Classification herein requires more than nominal recitation
of means or steps for controlling memory.
(5)
Note. This subclass and the subclasses thereunder also provide
for subject matter wherein static or dynamic storage forms part
of a digital data processing system.
(6)
Note. Subject matter classified herein may include nominal
recitations of reliability and availability in combination with memory accessing and control. The species
of reliability and availability related to data archiving,
backup, and device access limiting and security combined
with memory accessing and controlling
is classified herein. Other species of reliability and availability combined
with memory accessing and controlling
are classified elsewhere. See the SEARCH THIS CLASS, SUBCLASS notes
below.
(7)
Note. Memories known as display memory, display buffers, frame buffers, VRAMs,
etc., functioning in combination to store image data for
image processing are properly classified elsewhere.
Subject matter for interfacing between a graphics processor and
a memory is classified elsewhere.
See the SEARCH THIS CLASS, SUBCLASS notes and SEARCH CLASS notes
below for the information handling
subclasses relevant to memories acting on display data.
(8)
Note. Means or steps for accessing and controlling plural memory configurations (e.g., data farms, "library" systems, etc.)
including significant data processing are
classified here. Details of control systems for medium delivery
such as robotics or automated tape, cartridge, and platter selection
and delivery, however, are properly classified elsewhere under automated
control or another appropriate subclass in the respective device,
robotics, and generic control classes. In instances where there
is significant data processing and
significant details of medium delivery systems, classification should
be based on the hierarchy of classes and classified here.
(9)
Note. This subclass is directed to generic memory accessing
and control. Database accessing and retrieval is classified elsewhere.
See the SEARCH THIS CLASS, SUBCLASS notes below.
Communications: Electrical,
subclasses 825 through 825.98for controlling one or more devices to obtain a
plurality of results by transmission of a designated one of plural
distinctive control signals over a smaller number of communication
lines or channels, particularly subclasses 2.1-2.8 for path selection,
subclasses 3.1-3.9 for communication systems where status of a controlled
device is communicated, subclass 825.02 for tree or cascade selective
communication, subclasses 825.2-825.21 for synchronizing selective
communication systems, subclasses 825.52 and 825.53 for addressing,
and subclasses 825.57-825.69 for pulse responsive actuation.
Computer Graphics Processing and Selective Visual
Display Systems,
subclasses 530 through 574for memory organization and structure for storing
images to be displayed and subclasses 531-574 for interfacing between
a graphics processor and a memory.
Electricity: Electrical Systems and Devices,
subclasses 684+ for computer storage
component combined with housing or mounting arrangement having no data processing or calculating procedures.
Dynamic Information Storage or Retrieval,
subclasses 30.01 through 41.01,69, and 176-271, as appropriate, for subject matter
related to designation or selection of storage medium to be used
for storage and retrieval.
Multiplex Communications, for the simultaneous transmission of two or more signals
over a common medium, particularly
subclasses 351+ for time division multiplex (TDM) switching, subclasses
475+ for asynchronous TDM communications including addressing,
and subclasses 498+ for time division bus transmission.
Data Processing: Speech Signal Processing, Linguistics,
Language Translation, and Audio Compression/Decompression,
subclasses 2+ for memory control
scheme combined with linguistics.
Data Processing: Database and File Management
or Data Structures,
subclasses 1+ for database management and file management systems
including significant addressing, retrieval, or manipulation of
information contained within a database of a digital data
processing system or computer including
searching, query processing, information locating and retrieval techniques
from a file or database; subclasses 100+ for database schema types;
and subclasses 200+ for file maintenance operations, allocating
or deallocating memory space to files, garbage collection, and hierarchical
or tree filling systems.
Electrical Computers and Digital Data Processing
Systems: Input/Output,
subclasses 1+ for combinations of data transfers performed by
a peripheral (e.g., I/O processors, DMA, I/O controllers,
I/O adapters, etc.) between digital data processing systems
or computers and peripherals; subclasses 22+ for Direct
Memory Access (DMA) or direct data transfers to or from memory or
to or from other peripherals and for data transfers performed by
a peripheral between external components such as disk drives, peripheral
devices, etc., which involves I/O processing; and subclasses
100+ for connections within a single computer or digital
data processing system arrangement such as interfacing, bus arbitration,
bus expansion.
Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g., Processors),
subclasses 220+ for processing control and instruction processing,
per se, which often includes access to registers surrounding functional
units of a processor.
Error Detection/Correction and Fault Detection/Recovery,
subclasses 1+ for reliability and availability combined with
memory accessing and control not provided for herein (see the (
6 ) Note above).
Data Processing: Software Development, Installation,
and Management,
subclasses 151 through 161for software/program optimization of memory
usage or other resource usage (e.g., optimization by removing redundancy,
eliminating unnecessary memory accesses, etc.).
This subclass is indented under subclass 100. Subject matter wherein control of the memory or
the accessing thereof is adapted to the type of memory being
accessed.
(1)
Note. Structures and particulars of the memory device
itself are classified in the relevant device class.
(2)
Note. Subject matter included herein is directed to the specifics
of accessing technique employed to access and control the memory by computers, digital data processing systems, processors, or other users.
(3)
Note. The nature of data stored
in a memory (i.e., the information) does not make the memory "specific" within
the context of this and its indented subclasses (e.g., video or
image data, printer buffer, control datamemory,
etc.).
(4)
Note. Accessing and controlling of a multiport memory, per se, are classified elsewhere
in this class. See the SEARCH THIS CLASS, SUBCLASS notes below.
Electronic Digital Logic Circuitry,
subclasses 37+ for multifunctional or programmable logic (e.g.,
gate arrays) and subclasses 52+ and 104+ for generic
logic functions such as EXOR, AND, OR, NOT, and decoding.
Dynamic Information Storage or Retrieval,
subclasses 30.01 through 41.01,69, and 176-271, as appropriate, for subject matter
related to designation or selection of storage medium to be used
for storage and retrieval.
This subclass is indented under subclass 101. Subject matter including means or steps for accessing solid-state
randomly accessible nonvolatile memory (e.g.,
ROM).
Static Information Storage and Retrieval, appropriate subclasses for storage having a particular
internal cell structure (e.g.,
subclass 94 for read only (i.e., semipermanent) systems),
subclasses 189.011 for memory read/write
circuits, and subclasses 230.01+ for addressing circuits.
This subclass is indented under subclass 102. Subject matter including means or steps for accessing and
controlling programmable solid-state nonvolatile memory (e.g.,
PROM, EPROM, EEPROM, flash, etc.).
This subclass is indented under subclass 104. Subject matter including means or steps for accessing volatile memory requiring periodic refreshing (e.g.,
DRAM, Dynamic RAM, etc.).
This subclass is indented under subclass 105. Subject matter including specifics of coordinating refreshing
operations with other system operations.
(1)
Note. This subclass is proper for subject matter directed
to coordinating refresh scheduling with other system events, accesses,
requirements, etc., external to the memory cells.
However, coordinating the timing requirements within a memory cell or composite thereof is classified
elsewhere. See the SEARCH CLASS notes below.
Static Information Storage and Retrieval, appropriate subclasses for timing requirements at the cell
level and for storage having a particular internal cell structure
(e.g.,
subclass 222 for memory refreshing).
This subclass is indented under subclass 101. Subject matter comprising arrays of magnetizable rings as
the individual storage elements.
(1)
Note. In the 1960"s the term "core memory" referred exclusively
to memory with ferrite cores. Also
at that time, the main memory of
large systems were exclusively of this type. As the art progressed,
the term core memory became a holdover
to refer to the system"s main memory,
regardless of the actual type of memory being
used. Therefore, if core memory is
claimed, the specification should be checked to see if the memory is indeed core memory (i.e.,
ferrite memory) for classification
here; otherwise, it should be treated as solid-state memory and classified elsewhere.
This subclass is indented under subclass 101. Subject matter including memory of
the type where elements are addressed according to the stored contents
(e.g., associative memory, etc.).
This subclass is indented under subclass 101. Subject matter including memory of
the type where elements are arranged to serially pass the stored
contents from one location to an adjacent location, or for use in data format conversion within a digital data processing system.
(1)
Note. Employing shift registers as part of the system memory for transferring data within
a digital data processing system is
classified here; however, the specifics of the interconnections
and control of shift register memories is
classified elsewhere. See the SEARCH CLASS notes below.
(2)
Note. Although data format
conversion may form part of the overall combination in this subclass, data format conversion, per se, is classified
elsewhere. See the SEARCH CLASS notes below.
Electrical Pulse Counters, Pulse Dividers, or
Shift Registers: Circuits and Systems,
subclasses 64+ for shift registers and subclasses 107+ and 118+ for
counters.
This subclass is indented under subclass 109. Subject matter wherein the contents of a register may be
passed in a recirculating fashion among a group of adjacent registers
(e.g., ring buffers, barrel shifters, etc.).
This subclass is indented under subclass 101. Subject matter including accessing memory of the
type where a storage medium is moved relative to a transducer (e.g.,
magnetic or paper tape, punched cards, etc.).
(1)
Note. This and indented subclasses provide for dynamic storage
combined with significant digital data processing
system elements and functions.
Registers,
subclasses 375+ for various systems controlled by data bearing records,
subclasses 419+ for record controlled calculators, and
subclasses 435+ for coded record sensors.
This subclass is indented under subclass 111. Subject matter wherein devices employing a medium capable
of being accessed directly and by so doing skipping past portions
of the medium.
(1)
Note. For purposes of this definition, memory devices
known typically as disks, drums, etc., are considered to be of the
direct access type whereas tapes are not.
This subclass is indented under subclass 112. Subject matter wherein the DASD is used as a dedicated hierarchically
intermediate store or with a dedicated hierarchically intermediate store.
(1)
Note. Caching in this subclass is (a) being performed by
a DASD device or (b) being supplied by another device in combination
with a DASD. Caching, per se, is classified elsewhere.
This subclass is indented under subclass 112. Subject matter where a plurality of direct access devices
are arranged in an array and files or portions thereof are stored
on more than one of the direct access storage devices.
(1)
Note. This subclass is appropriate for redundant arrays of
inexpensive disks (RAID).
(2)
Note. See the (6) Note to subclass 100 for systems directed
to reliability and availability of DASDs. See the SEARCH CLASS notes
below.
This subclass is indented under subclass 101. Subject matter wherein the memory is
of the solid-state type and can be readily physically connected
and disconnected manually, without the aid of any tools, for temporary
or transient purposes (e.g., replaceable memory cartridges, smart
cards, etc.).
This subclass is indented under subclass 101. Subject matter wherein the memory is
of the solid-state type comprising one or more series of persistent
microscopically small magnetized bubbles on a thin film substrate.
This subclass is indented under subclass 100. Subject matter wherein the memory being accessed
or controlled is in an arrangement consisting of more than one ordered
level of memory.
This subclass is indented under subclass 117. Subject matter wherein portions of the data stored
in slower main memory are transferred to
faster memory between processor(s) and the main memory.
This subclass is indented under subclass 118. Subject matter employing plural cache memories arranged
between at least one processor and
at least one main memory.
This subclass is indented under subclass 119. Subject matter further comprising means or steps for employing
plural cache memories arranged at
the same ordinal level between at least one processor and
at least one main memory.
This subclass is indented under subclass 119. Subject matter further comprising means or steps for employing
plural cache memories where at least one of the caches is exclusively associated
with a respective one of a plurality of processors.
This subclass is indented under subclass 119. Subject matter further comprising means or steps for caching
at a plurality of different hierarchical levels (e.g., main cache
coupled to an on-chip cache).
This subclass is indented under subclass 119. Subject matter further comprising means or steps for employing
separate or partitioned cache(s) for separately storing portions
of instruction data and user data, respectively.
(1)
Note. This physical separation of instruction
data and user data is
often referred to as Harvard architecture in the art and associated
literature.
This subclass is indented under subclass 119. Subject matter wherein an individual cache system must announce
to other cache systems or check with other cache systems which may possibly
contain a copy of a given cached location prior to or upon modification
or appropriation of data at a given
cached location.
This subclass is indented under subclass 118. Subject matter further comprising means or steps using a
single cache dedicated to caching instruction
data.
Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g., Processors),
subclasses 200 through 219,220+ and 300 for instructional data processing,
particularly 216+ for instruction dependency checking
and resolution.
Static Information Storage and Retrieval,
subclasses 230.03 and 230.04 for subject matter including plural
banks or blocks and alternating between them.
This subclass is indented under subclass 118. Subject matter further comprising organizing a cache system
where any block in main memory can
be mapped to any block in the cache (fully associative) or where
the cache is divided into sets of blocks and individual blocks of
main memory are mapped to any of
the blocks of a particular corresponding set (that is, for example,
set associative).
This subclass is indented under subclass 118. Subject matter further comprising means or steps for dividing
the cache into independent sections or domains.
This subclass is indented under subclass 118. Subject matter further comprising means or steps for providing
caching functions to a plurality of processors from
single cache.
This subclass is indented under subclass 118. Subject matter further comprising caches composed of multiport memory thereby allowing simultaneous reads
from the cache by plural processors.
This subclass is indented under subclass 118. Subject matter including provisions for determining when
the contents of a cache location may be replaced with other data.
This subclass is indented under subclass 133. Subject matter where the determination is made based upon
the time since the last access to the contents of a given location.
This subclass is indented under subclass 118. Subject matter where selected data from
main memory are retrieved into the
cache prior to any request from the processor for
the selected data.
Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g., Processors),
subclass 205 for fetching, 207 for prefetching, and 233+ for
branch prediction.
This subclass is indented under subclass 138. Subject matter including provisions for marking selected
locations of main memory so that the
contents are not cached.
This subclass is indented under subclass 118. Subject matter wherein one access sequence to the cache memory is started before a prior access
sequence is completed.
This subclass is indented under subclass 118. Subject matter further comprising means or steps not specifically
covered above for assuring that the data stored
in the cache memory and those of
the main memory are either identical
or controlled so that stale and current data are
not confused with each other.
(1)
Note. The subject matter in this subclass is also called
cache consistency or cache currency in the art.
Data Processing: Database and File Management
or Data Structures,
subclasses 200 through 206for file and database maintenance systems including data coherency in database or file systems.
Error Detection/Correction and Fault Detection/Recovery,
subclasses 1+ for reliability and availability in digital data
processing systems, per se, including subclasses 5+ for
memory or peripheral subsystem affected fault recovery.
Data Processing: Presentation Processing of Document,
Operator Interface Processing, and Screen Saver Display Processing,
subclasses 255 through 272for developing or changing a document wherein one
or more elements of document are added, deleted, or modified, or
including means or steps for storing the resultant altered document
or the alterations.
This subclass is indented under subclass 141. Subject matter where, as contents of the cache are changed,
the changes are also posted to main memory substantially
simultaneously.
This subclass is indented under subclass 141. Subject matter where, as contents of the cache are changed,
the changes are not posted to main memory immediately,
but rather changes to a block are posted upon the occurrence of
a predetermined event.
This subclass is indented under subclass 141. Subject matter wherein coherency for each unit or block
of data includes associated identifier bit(s)
to indicate the validity status of an associated cached location.
(1)
Note. For this subclass, validity status bits can indicate
whether data are modified, valid,
dirty, etc.
This subclass is indented under subclass 141. Subject matter wherein each unit or block of memory or cache includes associated identifier bit(s)
to indicate ownership of or restricted access to the unit or block.
(1)
Note. For this subclass, access control bits can indicate
whether the associated cached location is exclusive, shared, read
only, locked, etc.
This subclass is indented under subclass 141. Subject matter further comprising cache memory monitoring
an associated address bus to determine
if access to a cached location occurs by another cache memory or other user (e.g., DMA, peripherals, etc.).
Electrical Computers And Digital Data Processing
Systems: Input/Output,
subclasses 100+ for system intraconnecting, particularly subclasses 107+ for
bus access regulating.
This subclass is indented under subclass 100. Subject matter wherein at least a portion of the memory being accessed or controlled is
solid-state memory that iscommon
to a plurality of users (e.g., a CPU and a DMA controller, multiple
CPUs, etc.) or a plurality of tasks (e.g., in a multitasking system)
or both.
Electrical Computers and Digital Processing Systems:
Multicomputer Data Transferring or Plural Processor Synchronization,
subclasses 213 through 216for a plurality of computers transferring data
through one or more memories accessible by the plurality of computers.
Electrical Computers and Digital Processing Systems:
Virtual Machine Task or Process Management or Task Management/Control,
subclasses 102 through 108for process scheduling involving balancing the
work load or resources, memory use, register use, resource availability,
time constraints, semaphores, and mutual exclusion mechanisms used
for programs or process synchronization.
This subclass is indented under subclass 147. Subject matter including means or steps for controlling
shared memory capable of supporting
a plurality of simultaneous read accesses.
Electrical Computers And Digital Data Processing
Systems: Input/Output,
subclasses 36+ for I/O access regulating; subclasses
107+ for access regulating and arbitration within a digital
data processing system; subclasses 200 through 244 for generalized
locking, polling, access arbitrating; and subclasses 260+ for interrupt
processing.
This subclass is indented under subclass 147. Subject matter including provisions for assigning priority
for use in handling simultaneous memory access
requests.
Electrical Computers and Digital Data Processing
Systems: Input/Output,
subclasses 36+ for I/O access regulating; subclasses
107+ for access regulating and arbitration within a digital data
processing system; and subclasses 200 through 269 for generalized
locking, polling, access arbitrating, and interrupt processing.
Electrical Computers and Digital Processing Systems:
Virtual Machine Task or Process Management or Task Management/Control,
subclass 103 for priority scheduling of process (e.g., deciding
which resources to use, deciding which jobs to do first and what
order to do them; scheduling constraints may include resource characteristics
such as performance, availability, data coherency, etc.).
Electrical Computers and Digital Data Processing
Systems: Input/Output,
subclasses 36+ for I/O access regulating; subclasses
107+ for access regulating and arbitration within a digital data
processing system; and subclasses 200 through 244 for generic access
locking, access regulating, or access arbitration in data processing system.
This subclass is indented under subclass 147. Subject matter further comprising means for dividing or
segmenting a given logical shared memory area
into independent sections or domains.
Data Processing: Database and File Management
or Data Structures,
subclasses 1+ for database management and file management systems
including significant addressing, retrieval, or manipulation of
information contained within a database of a digital data
processing system or computer including
searching, query processing, information locating and retrieval techniques
from a file or database; and subclasses 200+ for file maintenance
operations, allocating or deallocating memory space to files, garbage collection,
and hierarchical or tree filling systems.
Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g., Processors),
subclass 228 for processing control and instruction processing
for context preserving; subclass 229 for processing control and
instruction processing for mode switch or change.
Data Processing: Software Development, Installation,
and Management, appropriate subclasses for significant details of
the construction, analysis, or modification of computer languages.
Electrical Computers and Digital Processing Systems:
Virtual Machine Task or Process Management or Task Management/Control, appropriate subclasses for processing task management,
in particular
subclass 107 and 108 for multi-tasking and context switching.
Electrical Computers and Digital Processing Systems:
Interprogram Communication or Interprocess Communication (IPC), appropriate subclassesfor interprogram or interprocess communication.
This subclass is indented under subclass 100. Subject matter including particular means or steps for controlling memory accesses not specifically provided
for above.
Error Detection/Correction and Fault Detection/Recovery,
subclass 702 for memory access, subclasses 710+ for replacement
with spare memory component or portion of memory component, subclasses
763+ for memory testing and memory accessing with error
correction.
This subclass is indented under subclass 154. Subject matter including provisions for performing an access
operation where the contents of a given memory location
are read and then overwritten in a single access operation.
Static Information Storage and Retrieval,
subclasses 230.03 and 230.04 for subject matter including plural
banks or blocks and alternating between them.
This subclass is indented under subclass 154. Subject matter including banks or modules which are arranged
so that a given physical memory element
has access priority over another.
This subclass is indented under subclass 154. Subject matter including provisions for determining when
the data stored in a particular memory location may be replaced.
This subclass is indented under subclass 159. Subject matter wherein the determination is made based upon
the time since the last access to the contents of a given location.
This subclass is indented under subclass 154. Subject matter wherein the control technique prevents the
corruption, loss, alteration, or disclosure of data by
storing.
Electrical Computers and Digital Processing Systems:
Support,
subclasses 150 through 181for multiple computer communication using cryptography
and subclasses 187 and 188 for software program protection or computer
virus detection in combination with data encryption.
Error Detection/Correction and Fault Detection/Recovery,
subclasses 1+ for diagnostic testing or monitoring of a digital
data processing system for reliability purposes comprising power fail-safe
functions, fault detection, or anticipation of a failure; more specifically,
subclasses 5+ for memory or peripheral subsystem affected
recovery, subclass 42 for memory component fault, and subclass 54
for storage content error detection or notification, subclasses
5+ and 718+ for reliability and availability in
memory accessing and control such as isolating failed memory and
storing redundant data with recitation of the recovery, fault, or
failure.
Data Processing: Software Development, Installation,
and Management,
subclasses 168 through 172for software upgrading or updating and subclasses
174-178 for software installation including local and remote software
(e.g., operating system, application program, and other executable
program) loading, copying, or installing onto a target storage medium
such as a hard disk, tape drive, or other memory device.
Error Detection/Correction and Fault Detection/Recovery,
subclasses 5+ and 718+ for reliability and availability
in memory accessing and control such as isolating failed memory
and storing redundant data with recitation of the recovery, fault,
or failure.
Electrical Computers and Digital Data Processing
Systems: Input/Output,
subclasses 36+ for access regulating of peripheral to computer
or vice versa; subclasses 107+ for regulating access of
processors or memories to a bus; and subclasses 200 through 244 for
generic access locking, access regulating, or access arbitration
in data processing system.
Electrical Computers and Digital Processing Systems:
Support,
subclasses 182 through 186for system access control based on cryptographic
identification, and subclasses 187 and 188 for software program
protection or computer virus detection in combination with data
encryption.
This subclass is indented under subclass 163. Subject matter wherein authorization code information (e.g.,
password, key other than encryption key, etc.) is required for memory access.
(1)
Note. This subclass does not provide for cryptographic keys.
See below.
Data Processing: Financial, Business Practice,
Management, or Cost/Price Determination,
subclass 18 for handling security or user identification provision
to either prevent unauthorized use or access.
Electrical Computers and Digital Processing Systems:
Support,
subclass 187 and 188 for software program protection or computer
virus detection in combination with data encryption.
This subclass is indented under subclass 154. Subject matter including provisions for moving or copying data from one location in a given memory to another location in the given memory or another memory at
the same hierarchical level.
(1)
Note. This subclass does not provide for DMA. See below.
This subclass is indented under subclass 154. Subject matter including provisions for clearing or initializing
the contents of a given memory location.
(1)
Note. This subclass provides for setting a portion of memory to an initial condition (e.g.,
filling all locations with zeros).
Electrical Computers and Digital Processing Systems:
Support,
subclass 1 for digital data processing system initialization
or configuration (e.g., initializing, setup, configuration, or resetting)
allocating extended or expanded memory, speci device drivers, paths,
files, buffers, disk management, etc.; subclass 2 for loading initialization
program (e.g., booting, BIOS, IPL, bootstrap, etc.); and subclass
100 for reconfiguring (e.g., changing system settings) of system settings,
per se.
This subclass is indented under subclass 100. Subject matter including provisions for controlling or coordinating
the sequence of operations that make up a memory access.
Multiplex Communications,
subclass 507 wherein the clock frequency adjustment of one station
is based upon information about
status of clock signals originating at other stations of the system.
Electrical Computers and Digital Processing Systems:
Multicomputer Data Transferring or Plural Processor Synchronization,
subclass 248 for multicomputer synchronization in a network.
Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g., Processors),
subclasses 245 through 248for processing sequence control.
Electrical Computers and Digital Processing Systems:
Support,
subclasses 400+ for details relating to the timing control or timing
regulation of any one or combination of digital data processing
system components according to a periodic sequence of clock/ timing
pulses (e.g., synchronous time control, time delay, cycle control,
cycle steal, etc.).
Electrical Computers and Digital Processing Systems:
Virtual Machine Task or Process Management or Task Management/Control, appropriate subclassesfor task and process scheduling.
This subclass is indented under subclass 167. Subject matter further including means or steps wherein
multiple memory accesses are initiated substantially
simultaneously.
Electrical Computers and Digital Processing Systems:
Virtual Machine Task or Process Management or Task Management/Control,
subclass 107 and 108 for multitasking and time sharing/slicing.
This subclass is indented under subclass 167. Subject matter further including means or steps wherein
a first access to memory is initiated before
a second access is completed.
(1)
Note. Pipelined instruction data processing is
classified elsewhere. See the SEARCH THIS CLASS, SUBCLASS notes
below.
Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g., Processors),
subclasses 205+ for instruction fetching, subclasses 214+ for
instruction issuing, subclasses 233+ for branching instruction
processing.
Electrical Computers and Digital Processing Systems:
Virtual Machine Task or Process Management or Task Management/Control, appropriate subclassesfor task management and control related to process
or job execution.
This subclass is indented under subclass 100. Subject matter in which the allocation of memory space
is specified or the layout is automatically determined.
(1)
Note. Configuration at booting via software is classified
elsewhere in this class. See the SEARCH THIS CLASS, SUBCLASS notes
below.
(2)
Note. Assigning operating characteristics to peripherals is
classified elsewhere in this class. See the SEARCH THIS CLASS,
SUBCLASS notes below.
Data Processing: Database and File Management
or Data Structures,
subclasses 1+ for database management and file management systems
including significant addressing, retrieval, or manipulation of
information contained within a database of a digital data
processing system or computer including
searching, query processing, information locating and retrieval techniques
from a file or database; and subclasses 200+ for file maintenance
operations, allocating or deallocating memory space to files, garbage collection,
and hierarchical or tree filling systems.
Electrical Computers and Digital Processing Systems:
Multicomputer Data Transferring or Plural Processor Synchronization,
subclasses 220 through 222for network computer configuring.
Electrical Computers and Digital Data Processing
Systems: Input/Output,
subclasses 8+ for assigning operating characteristics to peripherals
or peripheral configuring and subclass 104 for utilizing a hardware
structure for providing to a digital data processing system component
the arrangement of the digital data processing system including
characteristics of the digital data processing system"s
components.
Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g., Processors),
subclass 228 for processing control and instruction processing
for context preserving, subclass 229 for processing control and
instruction processing for mode switch or change.
Electrical Computers and Digital Processing Systems:
Support,
subclasses 1+ for digital data processing system initialization
or configuration (e.g., initializing, set up, configuration, or resetting)
allocating extended or expanded memory, specifying device driver,
path, file, buffer, disk management, etc.; subclass 100 for reconfiguring
of system setting, per se.
Error Detection/Correction and Fault Detection/Recovery,
subclasses 3+ for reconfiguring in the event of a fault under
fault recovery, reliability, and availability.
Electrical Computers and Digital Processing Systems:
Virtual Machine Task or Process Management or Task Management/Control, appropriate subclasses for task management, in particular
subclass 104 for resource allocation (e.g., deciding how best
to use the available resources to get the job done) and also subclasses
107 and 108 for multitasking and context switching.
This subclass is indented under subclass 170. Subject matter comprising means or steps for allocating memory space based on the amount of storage
space required.
This subclass is indented under subclass 170. Subject matter comprising means or steps for allocating memory based on the size of each physical
solid-state memory.
This subclass is indented under subclass 170. Subject matter further comprising means for dividing or
segmenting a given logical memory into
independent sections or domains.
This subclass is indented under the class definition. Subject matter comprising means or steps for determining
or modifying a value which specifies a location in at least one memory.
(1)
Note. The subject matter of this subclass and the subclasses
thereunder includes, for example, virtual memory addressing,
address translation, translation look-aside buffers (TLBs), boundary
checking, and page-mode addressing.
(2)
Note. The subject matter also includes deriving new address data from existing address data.
(3)
Note. The location in memory may include data for forming further an address (e.g.,
address mapping is classified herein).
(4)
Note. Means or steps for addressing or for storing data in one or more memory cells
of a storage medium having one or more specific, internal cell elements
is classified elsewhere. See the SEARCH CLASS notes below.
through 116, for storage accessing and control for
various memory compositions (e.g.,
ROM, RAM, CAM, dynamic, detachable, bubble, etc.) with more than
nominal data processing.
Communications: Electrical,
subclasses 825.52 through 825.53for selective communication addressing and subclasses
14.1-14.69 for selective decoder matrix which may be used for control
or as a switching means.
Computer Graphics Processing and Selective Visual
Display Systems,
subclasses 530 through 574for processing indices to locations (or addresses)
of stored data elements in a computer graphic processing system.
Static Information Storage and Retrieval,
subclass 189.011 for read/write circuits and subclasses
230.01+ for addressing of addressable, static single
storage elements or plural elements of the same type.
Dynamic Information Storage or Retrieval, various subclasses for record carriers and systems wherein information
is stored and retrieved by interaction with a medium and there is relative
motion between a medium and a transducer. Particularly, see
subclasses 30.01 through 41.01for selective addressing of dynamic storage medium.
Multiplex Communications, appropriate subclasses for multiplex switching techniques
similar to addressing and the handling of memoryinformation signals (e.g.,
subclasses 351+ for packetized multiplexed communications).
Data Processing: Speech Signal Processing, Linguistics,
Language Translation, and Audio Compression/Decompression,
subclasses 2+ for memory control
scheme combined with linguistics.
Data Processing: Database and File Management
or Data Structures,
subclasses 1+ for database management and file management systems
including significant addressing, retrieval, or manipulation of
information contained within a database of a digital data
processing system or computer including
searching, query processing, information locating and retrieval techniques
from a file or database; subclasses 100+ for database schema types;
and subclasses 200+ for file maintenance operations, allocating
or deallocating memory space to files, garbage collection, and hierarchical
or tree filling systems.
Electrical Computers and Digital Data Processing
Systems: Input/Output,
subclasses 3 through 4for Input/Output addressing; subclass
9 for address assignment for configuring peripherals, subclasses
22-28 for direct memory accessing including addressing techniques;
and subclass 316 for system intra-connecting switching.
Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g., Processors),
subclasses 208+ for instruction decoding involving start or initial
address generation; subclass 230 for generating the address of the next
micro-instruction.
This subclass is indented under subclass 200. Subject matter wherein the value determination takes into
account a memory size constraint.
(1)
Note. This subclass will accept range or limit checking,
boundary crossing, and related memory boundary
issues (e.g., (a) handling a boundary fixed length field to accommodate data size or position and boundary checking
and (b) incrementing addresses within a page).
This subclass is indented under subclass 200. Subject matter including translating (i.e., converting) processormemoryaddress data to physical memoryaddress data through a mechanism which
defines a correspondence between the addresses.
(1)
Note. The subject matter in this and the indented subclasses
is aimed at determining a physical address using a mapping technique.
(2)
Note. Classification here is proper for direct mapping for
a segmented memory not being used
in a virtual memory system.
This subclass is indented under subclass 202. Subject matter wherein the mapping allows an application
to view available memory resources
as a uniform primary memory.
This subclass is indented under subclass 203. Subject matter wherein means or steps are utilized for optimizing
address determination by, for example, anticipating a next address
or prefetching addresses.
Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g., Processors),
subclasses 205+ for instruction fetching, subclass 207 for profetching
of instructions and 233+ for branch prediction.
This subclass is indented under subclass 204. Subject matter wherein a memory space
is employed for registering indexes and the like to real or physical
address spaces in a predicting or look-ahead arrangement.
(1)
Note. A directory table is a mechanism for storing virtual
(i.e., logical) to physical (i.e., real, absolute) address translation
entries that are used in combination with methods of predicting
or prefetching.
(2)
Note. DLAT is a term of art referring to Directory Look-Aside
Table; TLB is a term of art referring to Translation Look-Aside
Buffer.
This subclass is indented under subclass 203. Subject matter wherein directories (e.g., maps) are employed
for converting address data in a first
form (e.g., virtual, logical) to address data in
a second form (e.g., physical, absolute).
(1)
Note. This subclass and its indented subclasses are intended
for generalized applications of tables not classifiable in the combinations
above.
(2)
Note. This area also provides for mechanisms for storing
virtual (i.e., logical) to physical (i.e., real, absolute) address translation
entries that are of general use in virtual memory.
(3)
Note. This subclass will accept table walking which generally
requires accesses to main memory.
This subclass is indented under subclass 206. Subject matter wherein a memory space
is employed for registering indexes and the like to real or physical
address spaces.
(1)
Note. These mechanisms convert address
data from a virtual address to a physical address without
the need for accessing translation tables in main memory (e.g.,
utilizing cache for virtual to physical translation).
(2)
Note. DLAT is a term of art referring to Directory Look-Aside
Table; TLB is a term of art referring to Translation Look-Aside
Buffer.
This subclass is indented under subclass 203. Subject matter wherein portions of memory are organized
or managed in accordance with a predetermined mapping scheme.
(1)
Note. This subclass includes art directed to addressing variable-sized
pages, segments, and blocks.
This subclass is indented under subclass 202. Subject matter including compensating for situations when
addresses map to the same location (e.g., synonym problems or alias addresses).
This subclass is indented under subclass 200. Subject matter including address bus modifying,
multiplexing addresses, or adapting to various bus widths.
Electrical Computers and Digital Data Processing
Systems: Input/Output,
subclass 300 for bus extending or expanding and subclasses
305-317 for bus architectures.
This subclass is indented under subclass 200. Subject matter wherein bits are added or subtracted from
existing address data to generate other address data.
Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g., Processors),
subclasses 205+ and 207 and 233+ respectively.
This subclass is indented under subclass 200. Subject matter wherein data relevant
to an instruction and used by an instruction are used to form the
address.
Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g., Processors),
subclasses 200 through 219,220+ and 300 for instruction processing,
particularly subclasses 233 through 244 for branching instruction
processing.
This subclass is indented under subclass 200. Subject matter wherein microcode is stored in memory and particular addressing mechanisms at
the microinstruction level are employed.
Electrical Computers and Digital Processing Systems:
Processing Architectures and Instruction Processing (e.g., Processors), particularly
subclasses 200 through 219,220+ and 300 for instruction processing,
particularly 245+ for microsequencing processing; and
subclasses 1+ for digital data processing system architecture.
This subclass is indented under subclass 200. Subject matter wherein an address value (i.e., key other
than an encryption key) is manipulated to form an index value.
(1)
Note. This subclass does not provide for cryptographic keys.
See below.
Electrical Computers and Digital Processing Systems:
Support,
subclass 187 and 188 for software program protection or computer
virus detection in combination with data encryption.
This subclass is indented under subclass 200. Subject matter wherein values specifying memory locations
are determined according to a predetermined algorithm.
Static Information Storage and Retrieval,
subclasses 230.03 and 230.04 for subject matter including plural
banks or blocks and alternating between them.
Electrical Pulse Counters, Pulse Dividers, or
Shift Registers: Circuits and Systems, appropriate subclasses for generic pulse counting
circuits and systems.
This subclass is indented under subclass 200. Subject matter utilizing particular hardware that adds by
1, subtracts by 1, and multiplies or divides by 2n (where n is an
integer).
Electrical Pulse Counters, Pulse Dividers, or
Shift Registers: Circuits and Systems, appropriate subclasses for generic pulse counting
circuits and systems.
This subclass is indented under subclass 200. Subject matter wherein results from the interaction of two
or more other data provide the address
(e.g., generalized indirect addressing, indexing, prefixing, base + sag/tag + set,
bit insertion).
This subclass is indented under subclass 200. Subject matter having a memory space
of general utility for registering indexes and like data related
to address generation (e.g., fixed offsets, conditions, or status).
The E-subclasses in U.S. Class 711 provide for methods and
apparatus for addressing or allocating computer memory space including
space management and address translation. They also provide for
methods and means for protecting against unauthorized use of memory
and protection against loss of memory contents.
ACCESSING, ADDRESSING, OR ALLOCATING WITHIN MEMORY SYSTEMS OR
ARCHITECTURES (EPO):
This main group provides for methods and apparatus for addressing
or allocating computer memory space including space management and
address translation. It also provides for methods and means for
protecting against unauthorized use of memory and protection against
loss of memory contents. This subclass is substantially the same
in scope as ECLA classification G06F12/00.
Note: The Patent
and Trademark Depository Library Program (PTDLP) administers a nationwide
network of public, state and academic libraries designated as Patent and
Trademark Depository Libraries authorized by 35 U.S.C. 13 to: Disseminate
Patent and Trademark Information Support Diverse Intellectual Property
Needs of the Public. PTDL Contact Information
Note: For information/comments on electronic information products, such
as purchasing USPTO data, or to discuss system requirements for magnetic
tape products, contact:
KEY: =online
business system =fees =forms=help =laws/regulations =definition
(glossary)
The Inventors
Assistance Center is available to help you on patent
matters.Send questions about USPTO programs and services
to theUSPTO
Contact Center (UCC). You can suggest USPTO webpages
or material you would like featured on this section by E-mail
to the webmaster@uspto.gov.
While we cannot promise to accommodate all requests, your suggestions
will be considered and may lead to other improvements on the
website.