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| Title: |
Bit-systolic arithmetic arrays using dynamic differential gallium arsenide circuits
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| Author(s): |
Beagles, Grant; Winters, Kel; Eldin, A. G.
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| Abstract: |
A new family of gallium arsenide circuits for fine grained bit-systolic arithmetic arrays is introduced. This scheme combines features of two recent techniques of dynamic gallium arsenide FET logic and differential dynamic single-clock CMOS logic. The resulting circuits are fast and compact, with tightly constrained series FET propagation paths, low fanout, no dc power dissipation, and depletion FET implementation without level shifting diodes.
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| NASA Center: |
NASA (non Center Specific)
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| Publication Date: |
JAN 1, 1992
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| Document Source: |
CASI |
| Online Source: |
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| Document ID: |
19940017251
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| Accession ID: |
94N21724
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| Publication Information: |
Idaho Univ., The 1992 4th NASA SERC Symposium on VLSI Design, 11 p, Number of Pages = 11 |
| Price Code: |
A03 |
| Keywords: |
CMOS; FIELD EFFECT TRANSISTORS; GALLIUM ARSENIDES; LOGIC CIRCUITS; SYSTOLIC ARRAYS; VERY LARGE SCALE INTEGRATION; DIRECT CURRENT; IMAGE PROCESSING;
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| Notes: |
In Idaho Univ., The 1992 4th NASA SERC Symposium on VLSI Design 11 p (SEE N94-21694 05-33) |
| Accessibility: |
Unclassified; No Copyright; Unlimited; Publicly available; |
| Updated/Added to NTRS: |
2008-10-20 |
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