Open Competition 2 - Electronics and Photonics

Contact Planarization for Microlithographic Processes

Sponsor: Brewer Science, Inc.

• Project Performance Period: 10/1/2001 - 1/31/2004
• Total project (est.): $3,495,840.00
• Requested ATP funds: $2,000,000.00

Advances in integrated circuit (IC) capacity and complexity depend on increases in the density of semiconductor devices and layering of metal circuitry. Each layer must be made absolutely flat prior to the next lithography step to achieve desired device performance. To ensure flatness, manufacturers typically use chemical mechanical planarization (CMP), which is costly, slow, and wasteful of resources. Brewer Science plans to develop and demonstrate an automated processing technology that will improve flatness while reducing costs and environmental impacts. It also will enable faster throughput and better quality control than CMP. Bench-scale trials of "contact planarization" have been successful, but the approach needs to be refined and optimized to produce consistent results and automated to meet the needs of chip maufacturing. The process involves the application of a malleable coating on the surface of a chip; the coating then is pressed against an optically clear, flat surface and cured with ultraviolet light. The coating may be left in place or removed, leaving the flat substrate. The process can be used with a range of dielectric materials and is independent of feature size and density effects. In the two-year project, Brewer will develop and assess various coating materials, processes, and equipment. One of the greatest technical challenge will be to achieve defect-free pressing of the planarizing material against the optically flat surface and the subsequent separation, and to consistently overcome the hydrostatic and adhesive forces between the optically flat surface and wafer substrate. ATP support is needed due to the high technical risk associated with the technology, and because progress otherwise be made fast enough to meet the rapidly evolving needs of industry on internal funding alone. If successfully developed and commercialized, the new process will enhance productivity in the semiconductor industry and make it possible to increase circuit complexity for a small, incremental cost. CMP costs $8-10 per wafer layer; the new process is projected to cost only $2 per layer. As a result, U.S. semiconductor manufacturers will gain a significant edge on their offshore competitors, and consumers and others will benefit from more feature-rich designs in products ranging from household appliances and automobiles to medical, transportation, and weapons technology.

For project information:

Russell Hopper, (573) 364-0300
russ.hopper@brewerscience.com

ATP Project Manager

Purabi Mazumdar, (301) 975-4891
purabi.mazumdar@nist.gov