Project BriefOpen Competition 1 - Information TechnologyReconfigurable Infrastructure Platform for Systems-on-ChipsDevelop an infrastructure platform for system-on-a-chip (SoC) electronics that implements a new kind of reconfigurable embedded debug logic to detect and fix design errors after fabrication, enabling reduced design cycle time, bypassing manufacturing defects, and improving yields. Sponsor: DAFCA, Inc.1671 Worcester RoadSuite 303 Framingham, MA 01701
Consumer demand is rapidly driving the increased miniaturization and performance of electronic devices. The combination of new features and functionality with the relentless drive toward miniaturization - from cell phones and digital cameras to medical instruments - is causing manufacturers to integrate increasingly complex circuits in a new kind of semiconductor component called system-on-chip (SoC). An SoC incorporates almost all of a product's functionality on a single, large, tightly integrated microchip. Today's leading-edge semiconductor technologies, however, have reached the point where design errors and manufacturing defects are almost unavoidable. This lengthens manufacturing cycles, lowers yield, and limits device reliability. The welcomed advances in miniaturization have introduced a whole new set of problems for designers and manufacturers: If you design and build an SOC and it doesn't work, how do you figure out why? DAFCA, Inc., an electronic design automation (EDA) software company, believes that the solution is to create an intelligent infrastructure - internal instrumentation of the device - that is small enough to fit neatly inside and powerful enough to identify and solve most problems. The company's technology merges conventional ASIC (application-specific integrated circuit) technology with a new form of reconfigurable logic. This breakthrough technology enables chip designers to rapidly achieve working silicon and to reduce significantly the time-to-market of their end product. Silicon debug is an extremely difficult part of semiconductor device development. The functional units that were once accessible as discrete components to logic analyzers and oscilloscopes are now concealed inside the silicon, often below many layers of metal. Moreover, the inability to easily fix design errors in silicon further extends the debug cycle and is currently an unsolved problem. Finally, silicon debug is severely handicapped by ad-hoc efforts with no unifying process or integrated software suites. DAFCA's reconfigurable fabric provides enhanced controllability and observability of the internal SoC signals, and implements user-specified post-silicon debug logic. Furthermore, the platform allows designers to correct many errors by reconfiguring the fabric, hence avoiding foundry turnaround for bug-fixing. DAFCA is partnering with several vendors of widely-deployed pre-silicon verification and debug tools. As a result, silicon debug will have the familiar "look and feel" of simulation-based debug. Moreover, the company will incorporate third-party assertions and other debug mechanisms directly in its fabric, thereby accelerating the location, isolation, and discovery of the root-cause of bugs in silicon. Extending simulation debug methodologies to the post-silicon phase of chip development will compress the entire debug cycle from months to weeks. All of the SoC designs that fall into the 65 and 90nm node category and a third or more of the 130-180nm starts (devices with 1 million or more logic gates) represent a potential opportunity for reconfigurable infrastructure. This comprises roughly 1,750 design starts out of 5,600 ASICs and ASSPs (application specific standard products) currently in design each year. Two thirds of these designs will require some sort of silicon debug. The potential savings to the industry from improved yields and fewer design cycles alone are estimated at several billion dollars per year. Although DAFCA has funding to develop the basic technology that it envisions, the company requires ATP support to address the much tougher problem of incorporating complex design assertions into the basic reconfigurable system.
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