Pixel Readout Chip Development

The effort to develop a pixel readout chip for use at the Tevatron collider was begun at Fermilab in late 1997. Two generations of prototype readout devices (FPIX0 and FPIX1) have firmly established a basic front end design philosophy and readout architecture. The third generation chip, FPIX2, will be fabricated later this year. The design engineers are Abder Mekkaoui and Jim Hoff.

All of the FPIX chips have been designed to match the ATLAS prototype pixel sensors, with 50 micron x 400 micron pixels.

A Cautionary Tale (damage to pcb seen after radiation exposure):

Click here for photographs of a printed circuit board damaged after radiation exposure.

FPIX0 consists of a 12 column by 64 row array of pixel unit cells together with relatively simple digital logic that provides a zero-suppressed readout of the chip. FPIX0 was designed and implemented in HP 0.8 micron CMOS with three goals in mind:

1. establish a front end design appropriate for use at the Tevatron collider;
2. verify that the analog and digital sections of the chip can be isolated from one another so that deadtimeless operation is possible;
3. verify that coupling through the sensor is not a problem (in all FPIX designs, the top metal layer is used as a shield between the sensor and the readout chip).

FPIX0 chips bonded to ATLAS prototype sensors have been extensively tested both on the bench and in a pion beam.

Scope Pictures (illustrating timing requirements and mistakes which can be made)

FPIX0 Photographs

Initialization & Readout

FPIX1

FPIX1 consists of 18 columns of 160 rows each of pixel unit cells. It was fabricated in HP 0.5 micron CMOS. The FPIX1 front end design is very similar to FPIX0. FPIX1 is the first implementation of a high speed readout architecture designed to meet the needs of the BTeV experiment, which will use pixel hits as the basis of its trigger. FPIX1 chips have also been bonded to ATLAS prototype sensors and tested both on the bench and in a pion beam.


FPIX1 Photographs

Sketch of 8x2 module (w/FPIX1's)

FPIX2

Until December, 1998, the plan was to migrate the FPIX design to the radiation hard Honeywell 0.5 micron CMOS SOI process. In December, 1998, we modified our R&D plan to focus on implementation in a commercial 0.25 micron CMOS process. This decision was motivated by the results of RD49, which showed that commercial deep submicron CMOS devices can be made radiation hard. Fermilab engineers joined RD49 and we turned our focus to redesigning the FPIX front end with the constraints imposed associated with a lower voltage process and the need for enclosed geometry transistors and guard rings. The FPIX2 design is being done using design rules which allow for implementation either through CERN, or by Taiwan Semiconductor Manugacturing Corporation (TSMC).

FPIX2 Amplifier Noise - Discriminator Threshold

Abder Mekkaoui's Talk at "Pixel 2000"
      pdf format, ppt format, ps format